Digital Systems, Part 2: Digital Design-Course 2,

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Digital Systems, Part 2 Digital Design-Course
2, CHAPTER Three- Memory Programmable
Logic(Free Educational Material) Prepared by
Dr. Ashraf Aboshosha www.icgst.com,
www.icgst-amc.com,www.icgst-fze.com,
www.icgst-ees.comeditor_at_icgst.comTel.
0020-122-1804952Fax. [phone]
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Memory Programmable Logic
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Introduction

• Memory unit a collection of cells capable of
  storing a large quantity of binary information
  and
• to which binary information is transferred
  for storage
• from which information is available when
  needed for processing
• together with associated circuits needed to
  transfer information in and out of the device
• write operation storing new information
  into memory
• read operation transferring the stored
  information out of the memory
• Types of Memories
• Random-access memory(RAM) perform both the write
  and read operations.
• Read-only memory(ROM) perform only the read
  operation(Used in Programmable circuits)

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Random-Access Memory(RAM)

• Memory unit that can be written or read
• Memory is composed of words
• Word is a group of bits
• Byte is a group of 8 bits (Denoted B)
• Words can have one or more bytes a word of 32
  bits has 4 bytes
• Memory size is normally measured in bytes, e.g.,
  1024 bytes 1KB

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Random-Access Memory(RAM)

• The communication between a memory and its
  environment is achieved through data input and
  output lines, address selection lines, and
  control lines that specify the direction of
  transfer.

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Content of a memory

• Each word in memory is assigned an identification
  number, called an address, starting from 0 up to
  2k-1, where k is the number of address lines.
• The number of words in a memory with one of the
  letters K210, M220, or G230.
• 64K 216 2M 221
• 4G 232

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Read Write Operations

• Write to RAM
• Apply the binary address of the desired word
  to the address lines
• Apply the data bits that must be stored in
  memory to the data input lines
• Activate the write control
• Read from RAM
• Apply the binary address of the desired word
  to the address lines
• Activate the read control

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Timing Waveform

• CPU clock 50 MHz
• -cycle time 20 ns
• Memory access time 50ns
• -The time required to complete a read or write
  operation
• The control signals must stay active for at least
  50ns
• -3 CPU cycles are required

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Types of memories

• Access mode
• -Random access any locations can be accessed
  in any order
• - Sequential access accessed only when the
  requested word has been reached (ex hard disk)
• Operating mode
• -Static RAM (SRAM)
• -Dynamic RAM (DRAM)
• Volatile mode
• -Volatile memory lose stored information when
  power is turned off (ex RAM)
• -Non-volatile memory retain its storage after
  removal of power (ex flash, ROM, hard-disk, .)

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Memory Decoding

• RAM of m words and n bits mn binary storage
  cells
• SRAM cell stores one bit in its internal latch
• SR latch with associated gates, 4-6
  transistors
• DRAMs contain one MOS transistor and one
  capacitor per cell

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Memory Decoding
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Memory Decoding

• Coincident decoding

• Decoder with k inputs and 2k outputs requires 2k
  AND gates
• A 1K memory requires a 10x1024 decoder
• Use instead a 2-D selection patter and 1K
  requires two 5x32 decoders!
• Word is selected by coincidence of one X and one
  Y line

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Memory Decoding

• Address Multiplexing

Capacity 256x256 28x28 64K RAS Row
Address Strobe CAS Column Address Strobe
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Error Detection and Correction

• Memory arrays are often very huge
• -May cause occasional errors in data access
• Reliability of memory can be improved by
  employing error-detecting and correcting codes
• Error-detecting code only check for the
  existence of errors
• -Most common scheme is the parity bit
• Error-correcting code check the existence and
  locations of errors
• -Use multiple parity check bits to generate a
  syndrome that can indicate the erroneous bits
• -Complement the erroneous bits can correct
  the errors

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Hamming code

• One of the most common used in RAM was devised by
  R. W. Hamming (called Hamming code).
• In Hamming code
• k parity bits in n-bit data word, forming a
  new word of n k bits. Those positions numbered
  as a power of 2 are reserved for the parity bits.
• the remaining bits are the data bits.

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Humming code

• Ex. Consider the 8-bit data word 11000100. we
  include four parity bits with it and arrange the
  12 bits as follows
• Bit position 1 2 3 4 5 6 7 8 9
  10 11 12
• P1 P2 1 P4 1 0 0 P8 0 1
  0 0
• P1 XOR of bits(3,5,7,9,11) 1 ? 1 ? 0 ? 0 ?
  0 0
• P2 XOR of bits(3,6,7,10,11) 1 ? 0 ? 0 ? 1 ?
  0 0
• P4 XOR of bits(5,6,7,12) 1 ? 0 ? 0 ? 0 1
• P8 XOR of bits(9,10,11,12) 0 ? 1 ? 0 ? 0
  1

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Humming code

• The data is stored in memory together with the
  parity bit as 12-bit composite word.
• Bit position 1 2 3 4 5 6 7 8 9
  10 11 12
• 0 0 1 1 1 0 0 1 0 1 0
  0
• When read from memory, the parity is checked over
  the same combination of bits including the parity
  bit.
• C1 XOR of bits(3,5,7,9,11)
• C2 XOR of bits(3,6,7,10,11)
• C4 XOR of bits(5,6,7,12)
• C8 XOR of bits(9,10,11,12)

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Humming code

• A 0 check bit designates an even parity over the
  checked bits and a 1 designates an odd parity.
• Since the bits were stored with even parity, the
  result,
• C C8C4C2C1 0000, indicates that no error has
  occurred.
• If C ? 0, then the 4-bit binary number formed by
  the check bits gives the position of the
  erroneous bit.

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Humming code

• Example
• Bit position 1 2 3 4 5 6 7 8 9
  10 11 12
• 0 0 1 1 1 0 0 1 0
  1 0 0 No error
• 1 0 1 1 1 0 0 1 0 1
  0 0 Error in bit 1
• 0 0 1 1 0 0 0 1 0 1
  0 0 Error in bit 5
• Evaluating the XOR of the corresponding bits, get
  the four check bits
• C8 C4 C2 C1
• For no error 0 0 0 0
• with error in bit 1 0 0 0 1
• with error in bit 5 0 1 0 1

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Hamming code

• The Hamming Code can be used for data words of
  any length.
• Total bit in Hamming Code is n k bits, the
  syndrome value C consists of k bits and has a
  range of 2k value between 0 and 2k - 1. the range
  of k must be equal to or greater than n k,
  giving the relationship
• 2k-1 n k

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Single-Error correction, Double-Error detection

• The Hamming Code can detect and correct only a
  single error.
• By adding another parity bit to the coded word,
  the Hamming Code can be used to correct a single
  error and detect double errors. Becomes
  001110010100P13.
• 001110010100 P13 ? 001110010100 1
• P XOR( 001110010100 1 )
• if P 0, the parity is correct (even parity),
  but if P 1, then the parity over the 13 bits is
  incorrect (odd parity).
• the following four cases can occur

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Single-Error correction, Double-Error detection

1. If C 0 and P 0, no error occurred
2. If C ? 0 and P 1, a single error occurred that
   can be corrected
3. If C ? 0 and P 0, a double error occurred that
   is detected but that cannot be corrected
4. If C 0 and P 1, an error occurred in the P13
   bit

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Read-Only Memory (ROM)

• ROM
• memory device in which permanent binary
  information is stored
• Binary information must be specified by the
  designer
• It then is embedded in the unit to form the
  required interconnection pattern
• nonvolatile

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Example (32 x 8 ROM)

• It Consists of
• 5-to-32 decoder
• 8 OR gates
• Each of 8 OR gates have 32 inputs
• 32x8 internal programmable connections

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Example (32 x 8 ROM)

• Programmable intersection
• -crosspoint switch
• Two conditions
• close two lines are connected
• open two lines are disconnected
• Implemented by fuse
• normally connects the two points
• opened or blown by applying a high voltage
  pulse
• A7(I4,I3,I2,I1,I0) S(0,2,3,,29)

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Combinational Circuit Implementation

• ROM uses a decoder for address and decoder gives
  minterms
• Outputs use OR gates thus ROM can be seen as
• -A storage device
• -Combinational circuit implementing Boolean
  functions
• Implementing combinational circuits by ROM needs
  only the ROM truth table
• connect the crosspoints representing the
  minterms
• no internal logic diagram is needed
• Procedures
• 1. Determine the size of ROM
• 2. Obtain the programming truth table
• 3. Blow the fuse pattern

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Example f(x)X2

• Accept a 3-bit number and generate an output
  number equal to the square of the input number
• 3 inputs and 6 outputs
• We can find that
• Output B0 is always equal to input A0
• output B1 is always 0
• Minimum size ROM 3 inputs and 4 outputs
• 8x4 ROM

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Types of ROM

• 4 methods to program ROM paths
• mask programming ROM
• customized and filled out the truth table
  by customer and masked by manufacturers during
  last fabrication process
• costly economical only if large quantities
• PROM Programmable ROM
• PROM units contain all the fuses intact
  initially
• Fuses are blown by application of a
  high-voltage pulse to the device through a
  special pin by special instruments called PROM
  programmers
• Written/programmed once irreversible

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Types of ROM

• EPROM erasable PROM
• floating gates served as programmed
  connections
• When placed under ultraviolet light, short
  wave radiation discharges the gates and makes the
  EPROM returns to its initial state
• reprogrammable after erasure
• EEPROM electrically-erasable PROM
• erasable with an electrical signal instead
  of ultraviolet light
• longer time is needed to write
• flash ROM limited times of write
  operations

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Combinational PLDs

• A combinational PLD is an integrated circuit with
  programmable gates divided into an AND array and
  an OR array to provide an AND-OR sum of product
  implementation.

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Programmable Logic Array (PLA)

• Programmable Logic Array (PLA)
• an array of programmable AND gates
• can generate any product terms of the
  inputs
• an array of programmable OR gates
• can generate the sums of the products
• only the needed product terms are generated
  (not all)
• more flexible than ROM use less circuits
  than ROM

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Programmable Logic Array (PLA)

• Size of PLA specified by of inputs, product
  terms and outputs
• n inputs, k product terms and m outputs
• n buffer-inverter gates, k AND gates, m OR
  gates, and m XOR gates
• typical PLA may have 16 inputs, 48 product
  terms and 8 outputs
• Designing a digital system with a PLA
• reduce the number of distinct product terms
• the number of literals in a product is not
  important
• Implementing PLA
• Mask programmable PLA submit a PLA program
  table to the manufacturer
• field programmable (FPLA) by commercial
  hardware programmer unit

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Programmable Logic Array (PLA)

• Example AND/OR/XOR
• F1 AB' AC A'BC'
• F2 (AC BC)'
• XOR gates can invert the outputs
• invert connected to 1
• not change connected to 0
• PLA programming table 3 sections
• 1. list the product terms
• 2. specify the required paths between inputs
  and AND gates
• 3. specify the paths between the AND and OR
  gates
• Specifying the fuse map and
• submitted to the manufacturer

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Programmable Array Logic (PAL)

• PAL has a fixed OR array and a programmable AND
  array
• -Easier to program but not as flexible as PLA
• Each input has a buffer-inverter gate
• One of the outputs is fed back as two inputs of
  the AND gates
• Unlike PLA, a product term cannot be shared among
  gates
• -Each function can be simplified by itself
  without common terms

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(PAL) Example

• Implement the following functions
• w(A,B,C,D) S(2,12,13)
• x(A,B,C,D) S(7,8,9,10,11,12,13,14,15)
• y(A,B,C,D) S(0,2,3,4,5,6,7,8,10,11,15)
• z(A,B,C,D) S(1,2,8,12,13)
• Simplify the functions
• w ABC' A'B'CD'
• x A BCD
• y A'B CD B'D'
• z ABC' A'B'CD' AC'D' A'B'C'D w
  AC'D' A'B'C'D

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Sequential Programmable Devices

• Sequential programmable devices
• combinational PLD flip-flops
• perform a variety of sequential-circuit
  functions
• Three major types
• Sequential (or simple) programmable logic device
  (SPLD)
• field-programmable logic sequencer (FPLS)
• Complex programmable logic device (CPLD)
• Field programmable gate array (FPGA)
• Many commercial vendor-specific variants and
  internal logic of these devices is too complex to
  be shown here

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SPLD

• Each section of an SPLD is called a macrocell.
• A macrocell is a circuit that contains a
  sum-of-products combinational logic function and
  an optional flip-flop.
• We will assume an AND-OR sum of products but in
  practice, it can be any one of the two-level
  implementation presented before (PLA or PAL).

Fig. Basic macrocell logic
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CPLD

• A typical SPLD has from 8 to 10 macrocells within
  one IC package. All the flip-flops are connected
  to the common CLK input and all three-state
  buffers are controlled by the EO input.
• The design of a digital system using PLD often
  requires the connection of several devices to
  produce the complete specification. For this type
  of application, it is more economical to use a
  complex programmable logic device (CPLD).

• A CPLD is a collection of individual PLDs on a
  single integrated circuit.

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Field-Programmable Gate Array (FPGA)

• The basic component used in VLSI design is the
  gate array.
• A Gate Array consists of a pattern of gates
  fabricated in an area of silicon that is repeated
  thousands of times until the entire chip is
  covered with the gates.
• FPGA Field-Programmable Gate Array
• Field-Programmable means user can program it in
  his own location.
• FPGA
• -Easier to use and modify
• -Getting popular for fast and reusable prototyping

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Field-Programmable Gate Array (FPGA)

• A typical FPGA consists of an array of hundreds
  or thousands of configurable logic blocks (CLB)
• CLBs are connected to each other via
  programmable interconnections
• CLBs are surrounded by I/O blocks for basic
  communication with outside world.
• CLBs consists of look-up tables, multiplexers,
  gates, and flip flops
• look-up table
• is a truth table stored in a SRAM
• provides the combinational circuit functions
  for the logic block.
• It is like a ROM implemented as SRAM

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Field-Programmable Gate Array (FPGA)
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End
Thank you