Razor: A Low Power Processor Design

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Razor A Low Power Processor Design

• Presented By -
• Murali Dharan

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Power Aware Computing

• Primary concern in design of processors and SoCs
• Paradox of need of higher clock frequencies and
  low power designs
• f a Vdd
• E SCV2dd VddIleakT

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Solution

• Dynamic Voltage Scaling (DVS)
• Periods of low processor utilization exploited by
  lowering clock frequency
• Critical supply voltage
• Min. supply voltage resulting in correct
  operation
• Should be sufficient to factor in global and
  local variations

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Voltage Margins

• Process Margin
• Result from manufacturing variations
• Ambient Margin
• Slower circuit operations at higher temperatures
• Noise Margin
• Safeguard against different noise sources

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Basic Idea Proposed

• Tune the supply voltage by monitoring the error
  rate during operation
• Accounts for both global and local variations
• Eliminates need for Voltage Margins
• Sub critical voltage cause trade off between
  error recovery and power savings
• Savings up to 64.2 with penalty of lt3

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Implementation of Error Correction
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Experimental Results
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Prototype Implementation
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Energy Optimal Characteristics
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Future Research Areas

• Implementation of Razor Technology in the design
  of Control Logics
• Implementation of Razor Technology in the design
  of Memories

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References

• Making Typical Silicon Matter with Razor
• Todd Austin, David Blaauw, Trevor Mudge
  University of Michigan Krisztián Flautner ARM
  Ltd.
• Razor A Low Power Pipeline Based on
  Circuit-Level timing Speculation
• Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay
  Pant, Rajeev Rao, Toan Pham, Conrad Ziesler,
  David Blaauw, Todd Austin, Trevor Mudge Advanced
  Computer Architecture Lab University of Michigan
  and Krisztián Flautner ARM Ltd.
• IEEE Spectrum Feb. 2008 Edition Intel and ARM
  are Exploring Self-Correction Schemes to Boost
  Processor Performance and Cut Power by Neil
  Savage