Microprocessor-based Systems Course 3

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Microprocessor-based SystemsCourse 3

• A (simple) computer structure

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Instruction format
Operation code
- Without explicit operands
- With one operand
Operand1 - Address
Operation code
Operand1 - Address
Operation code
Operand2 - Address/Data
- With 2 operands
Operand1 - Address
Operation code
Operand2 - Address/Data
Result - Address
- With 2 operands and a result
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Addressing modes

• How the operand is determined
• Immediate addressing for constants
• MOV AX, 1234h
• Direct addressing for simple variables
• SUB BX, 100h
• Indexed addressing for vectors
• ADD SI500h, AX
• Based addressing for records
• AND DX, BX200h
• Mixed (based and indexed) for complex data
  structures
• OR CX, SIBX100h

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The instruction set of a simple computer
Op. code 0 0 0 1 1 0 1 1
7 6
5 0
7 6 5 4 3 2 1 0
Op. code


Address field
0 0 0 0 0 1 . . . 1 1 1
NOP 00 000 xxx -
CLA 00 001 xxx A0
CPL 00 010 xxx ANot A
SHR 00 011 xxx AAgtgt1
SHL 00 100 xxx AAltlt1
SKIPO 00 101 xxx If A01 NP
SKIPN 00 110 xxx If A71 NP
STOP 00 111 xxx Stop the clock
Instruction Instr. code Explanations
JMP 01 addr NPaddr
ADD 10 addr AAMaddr
MEM 11 addr MaddrA
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The general scheme of a simple computer
Address display
STOP
START
Clock gen.
Sel_Op
Sel_I/D
Ld_IR
IR instruction reg.
CLK
M U X
INIT
M
Phase gen.
OC
OC/Addr
WrM
UAL
1
0
Decoder and comand block
Man/Auto
MUX
LdPC
Program counter
IncPC
micocomands
SHR
A
Ld_A
MUX
Man/Auto
SHL
RstA
Front panel
Addr. switches Data switches
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Decomposition of instructions into phases
INIT
I1
Sel_I/D0 Ld_IR
I2
IncPC
E1
E1
SHR
SHL
STOP
JMP
MEM
NOP
CLA
CPL
ADD
SKIPO
SKIPN
Sel_I/D1 Sel_op0
1
1
Sel_I/D1
Sel_op1
LdPC
RstA
A0
A7
IncPC
IncPC
0
0
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
Sel_I/D1
LdA
SHR
SHL
STOP
WrM
LdA
7
Phase generator (PG), Instruction decoder (ID)
and Command and control block (CCB)
RI
7 6
5 4 3
2 1 0
2
3
DEC
11
MEM
JMP
DEC
ADD
NOP
Stop
a. Phase generator
b. Instruction decoder
b. Implementation of the Sel_I/D cmd.
a. The contro and command block
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Sequential execution of instructions (Scalar
architecture)

• Execution phases of an instruction
• Instruction fetch (IF)
• Instruction decode (ID)
• Execution (Ex)
• Memory operation (Mem)
• Write back (Wr)
• CPI 5

IF
ID
Ex
Me
Wr
IF
ID
Ex
Me
Wr
IF
ID
Ex
Me
Wr
Instr. 1
Instr. 2
Instr. 3
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Parallel instruction execution on a pipeline
architecture (assembly line)
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Example of a pipeline architecture
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Hazard cases in pipeline architecture

• Data hazard
• Data dependency between consecutive instructions
• Solutions
• Idle states, multiple registers, instruction
  reordering

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Hazard cases in pipeline architecture

• Control hazard
• Caused by jump/branch instructions
• Solutions branch prediction, memorize previous
  jumps

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Hazard cases in pipeline architecture

• Structural hazard
• Two different phases of consecutive instructions
  require the same structural unit (e.g. ALU,
  memory, etc.)
• Solutions Idle states, instruction reordering,
  multiple structural units (e.g. multiple
  execution units, ALUs, data memory and
  instruction memory)

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Superscalar and superpipeline architectures
T1 T2 T3 T4 T5 T6
instr. i IF ID Ex Mem Wr
a. Superscalar architecture CPI1/2
instr. i1 IF ID Ex Mem Wr
instr. i2 IF ID Ex Mem Wr
instr. i3 IF ID Ex Mem Wr
T1 T2 T3 T4 T5 T6
instr. i IF ID Ex Mem Wr
b. Superpipeline architecture CPI1/2
instr. i1 IF ID Ex Mem Wr
instr. i2 IF ID Ex Mem Wr
instr. i3 IF ID Ex Mem
Wr
Comparison between superscalar and superpipeline
architectures
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Scheduling instruction execution

• Objective reordering instruction execution in
  order to avoid hazard situations and increase
  performance
• Static scheduling
• Reordering in the compilation phase
• Instructions are grouped in Very Long Instruction
  Words
• VLIW Very Long Instruction Word
• Dynamic scheduling
• Reordering during the execution of a program
• Techniques data flow analysis, dependency trees,
  branch predictions