CSE 502 Graduate Computer Architecture Lec 18-19

1
CSE 502 Graduate Computer Architecture Lec
18-19 Directory-Based Shared-Memory
Multiprocessors MP Synchronization

• Larry Wittie
• Computer Science, StonyBrook University
• http//www.cs.sunysb.edu/cse502 and lw
• Slides adapted from David Patterson, UC-Berkeley
  cs252-s06

2
Review Assignment

• Caches contain all information on state of cached
  memory blocks
• Snooping cache over shared medium for smaller MP
  by invalidating other cached copies on write
• Sharing cached data ? Coherence (values returned
  by a read), Consistency (when a written value
  will be returned by a read)
• Reading Assignment Finish Chap. 4 MPs and start
  Chap 5 Memory Hierarchies.

3
Outline

• Review
• Directory-based protocols and examples
• Synchronization
• Relaxed Consistency Models
• Fallacies and Pitfalls
• Cautionary Tale
• Conclusion

4
A Cache Coherent System Must

• Provide set of states, state transition diagram,
  and actions
• Manage coherence protocol
• (0) Determine when to invoke coherence protocol
• (a) Find info about state of block in other
  caches to determine action
• whether need to communicate with other cached
  copies
• (b) Locate the other copies
• (c) Communicate with those copies
  (invalidate/update)
• (0) is done the same way on all systems
• state of the line is maintained in the cache
• protocol is invoked if an access fault occurs
  on the line
• Different approaches distinguished by (a) to (c)

5
Bus-based Coherence

• All of (a), (b), (c) done through broadcast on
  bus
• faulting processor sends out a search
• others respond to the search probe and take
  necessary action
• Could do it in scalable network too
• broadcast to all processors, and let them respond
• Conceptually simple, but broadcast does not scale
  with p
• on bus, bus bandwidth does not scale
• on scalable network, every fault leads to at
  least p network transactions
• Scalable coherence
• can have same cache states and state transition
  diagram
• different mechanisms to manage protocol

6
Scalable Approach Directories

• Every memory block has associated directory
  information
• keeps track of copies of cached blocks and their
  states
• on a miss, find directory entry, look it up, and
  communicate only with the nodes that have copies
  if necessary
• in scalable networks, communication with
  directory and copies is through network
  transactions
• Many alternatives for organizing directory
  information

7
Basic Operation of Directory
k processors (or k snoopy nodes). With
each cache-block in memory k presence-bits, 1
dirty-bit With each cache-block in cache
1 valid bit, and 1 dirty (owner) bit

• Read from main memory by processor i
• If dirty-bit OFF then read from main memory
  turn pi ON
• If dirty-bit ON then recall line from dirty
  proc (cache state to shared) update memory turn
  dirty-bit OFF turn pi ON supply recalled data
  to i
• Write to main memory by processor i
• If dirty-bit OFF then supply data to i send
  invalidations to all caches that have the block
  turn dirty-bit ON turn pi ON
• If dirty-bit ON then recall line from dirty
  proc (cache state to invalid) update memory
  supply recalled data to i send invalidations to
  all caches that have the block leave dirty-bit
  ON turn pi ON

8
Directory Protocol

• Similar to Snoopy Protocol Three states
• Shared 1 processors have data, memory
  up-to-date
• Uncached only in memory no processor has it
• not valid in any cache
• Exclusive 1 processor (owner) has data in its
  cache or Dirty memory copy is out-of-date
• In addition to cache state, directory must track
  which processors have data when in the shared
  state (usually bit vector, 1 if processor has
  copy)
• Keep it simple(r)
• Writes to non-exclusive data (exclusive changes
  can be private) ? write miss
• Processor blocks until access completes
• Assume messages received and acted upon in order
  sent

9
Directory Protocol

• No bus and do not want to broadcast across
  network
• shared interconnect no longer is a single
  arbitration point
• all messages have explicit responses
• Terms typically 3 processors involved
• Local node where a request originates
• Home node where the memory location of an
  address resides
• Remote node has a copy of a cache block, whether
  exclusive or shared
• In example messages on next slide P processor
  number, A address

10
Directory Protocol Messages (Fig 4.22)

• Message type Source Destination Msg Content
• Read miss Local cache Home directory P, A
• Processor P reads data at address A make P a
  read sharer and request send data block to P
• Write miss Local cache Home directory P, A
• Processor P has a write miss at address A make
  P the exclusive owner and request old data for P
• Invalidate Home directory Remote caches A
• Invalidate a shared copy at address A
• Fetch Home directory Remote owner cache A
• Fetch the block at address A and send it to its
  home directorychange the state of A in the
  remote cache to shared
• Fetch/Invalidate Home directory Remote owner
  cache A
• Fetch the block at address A and send it to its
  home directory invalidate the block in the
  remote ex-owner cache
• Data value reply Home directory Local cache
  Data
• Return a data value from the home memory (read
  miss response)
• Data write back Remote cache Home directory A,
  Data
• Write back a data value for address A (invalidate
  or sharer response)

11
Implementing a Directory

• We assume operations atomic, but they are not
  reality is much harder must avoid deadlock when
  run out of buffers in network (see Appendix E)
• Optimizations to lessen network traffic, shorten
  latencies, or work by (bottleneck) directory PU
• For read-miss or write-miss of Exclusive
  cacheblock send data directly to requestor from
  owner instead of owner sending to memory and then
  memory sending to requestor
• For read-miss or write-miss of Exclusive
  cacheblock let directory send cacheblock owner
  id to requesting remote node and let requestor
  send message to owner to lessen work by directory
  (see next slide)
• For write-miss of Shared ( non-modified) block
  let directory send cacheblock value and list of
  sharing nodes to requestor and let requestor send
  invalidate requests to all nodes with a
  cacheblock copy to lessen work by directory (see
  next slide)

12
Example Directory Protocol (1st Read)
Read pA
P1 pA
M
Dir ctrl
P1

P2

ld vA -gt rd pA pA is page for add A
13
Example Directory Protocol (Read Share)
P1 pA
M
Dir ctrl
P2 pA
P1

P2

ld vA -gt rd pA
ld vA -gt rd pA
14
Example Directory Protocol (Wr to shared)
D for dirty block, modified from memory copy
P1 pA
EX
M
Dir ctrl
P2 pA
P1

P2

st vA -gt wr pA
15
Example Directory Protocol (Wr to Ex)
D for dirty block, modified from memory copy
P2 pA EX
M
Dir ctrl
P1

P2

st vA -gt wr pA
Inv/_
16
Basic Directory Transactions To Let Remote CPU Do
Much Coherency Work For Directory
17
A Popular Middle Ground

• Two-level hierarchy
• Individual nodes are multiprocessors, connected
  non-hierarchically
• e.g. mesh of SMPs
• Coherence among nodes is directory-based
• directory keeps track of nodes, not individual
  processors
• Coherence within nodes is snooping (or directory)
• orthogonal, but needs a good interface of
  functionality
• SMP on a chip support external directory snoop
  internally?

18
Synchronization

• Why Synchronize? Need to know when it is safe for
  different processes to use shared data (or code)
• Issues for Synchronization
• Need uninterruptable instruction to fetch and
  update memory (an atomic operation)
• User level synchronization operation using this
  primitive
• For large scale MPs, synchronization can be a
  bottleneck need techniques to reduce system
  overhead from contention for same lock by several
  processors and the latency of synchronization

19
Uninterruptable Instructions to Fetch and Update
Memory Values Used as Locks

• Atomic exchange interchange a value in a
  register for a value in memory
• 0 ? synchronization variable is free
• 1 ? synchronization variable is locked and
  unavailable
• Set register to 1 swap
• New value in register determines success in
  getting lock 0 if processor (PU) succeeded in
  setting the lock (PU was first) 1 if another
  processor had already claimed access
• Key is that exchange operation is indivisible by
  other stores
• Test-and-set sets(gt1) a lock value and tests
  prior lock value to see if PU has control of
  locked data (or code)
• 0 gt synchronization variable was free, so now
  owned by this PU
• 1 gt synchronization variable is owned
  (previously set) by another
• Fetch-and-increment returns the prior value of a
  memory location atomically increments it in
  memory
• Use to give PU unique pointer to job in a task
  queue

20
Uninterruptable Instruction Pair LL SC to Fetch
and Update Memory Atomically

• Hard to have read write in 1 instruction use 2
  instead
• Load linked (or load locked) store
  conditional
• Load linked (ll) returns the initial value
• Store conditional returns 1 to new value reg if
  it succeeds (no other store to same memory
  location since preceding ll) and 0 otherwise.
• Example doing atomic swap (exch) with LL SC
• try mov R3,R4 put new exchange value in
  R3 ll R2,0(R1) load linked value from
  lockgtR2 sc R3,0(R1) store conditional if
  same, R3gtlock, 1gtR3 beqz R3,try retry if
  sc not store R3 value (so just 0gtR3) mov R4,R2
  put loaded prior lock value into R4
• Example doing fetch increment with LL SC
• try ll R2,0(R1) load linked value from
  lock ctrgtR2 addi R2,R2,1 increment by 1
  (OK, since fast if regreg) sc R2,0(R1)
  store conditional if same, ctr1gtctr, 1gtR3
  beqz R2,try retry if store failed (not
  store ctr1, 0gtR2)

21
User-Level Synchronization-Operation Using An
Atomic Exchange Primitive

• Spin locks processor continuously tries to
  acquire lock, spinning around a loop trying to
  find the lock free (0)testset li R2,1 lockit
  exch R2,0(R1) atomic exchange bnez R2,lockit
  already locked?
• What about MP (multiprocessor) with cache
  coherency?
• To avoid latency of accessing main memory,
  should spin on cache copy
• Processors are likely to get cache hits for often
  used lock variables
• Problem exchange includes a write, which
  invalidates all other copies and generates
  considerable bus traffic
• Solution start by simply repeatedly reading the
  variable when it changes, then try exchange
  (test and testset)
• try li R2,1 lockit lw R3,0(R1) load
  var bnez R3,lockit ? 0 ? not free ?
  spin exch R2,0(R1) atomic exchange bnez R2,t
  ry already locked?

22
Another MP Issue Memory Consistency Models

• What is consistency? When must a processor see
  the new value? e.g., the results of this code
  seem clear, but
• P1 A 0 P2 B 0
• B1 B A2 A
• ..... .....
• A 1 B 1
• L1 if (B 0) ... L2 if (A 0) ...
• Is it impossible for both L1 L2 if conditions
  to be true?
• What if the write invalidate for A1 on P1 is
  delayed in reaching P2, but both P1 P2 continue
  on to execute their if statements L1 L2?
• Memory consistency models What are rules if
  accesses to different shared values (e.g., A B)
  can cause errors?
• (Safe) sequential consistency (SC) the result of
  any execution is the same as if all memory (read
  and write) accesses of each processor were kept
  in order and the accesses among different
  processors were interleaved in some order ? all
  assignments done before the ifs above.
• SC delay all memory accesses until all caches
  complete all invalidates.

23
Relaxed Memory Consistency Models

• Relaxed schemes run faster than always-safe
  sequential consistency
• Not an issue for most parallel programs they are
  synchronized.
• A program is synchronized if all accesses to
  shared data are ordered by (slow) synchronization
  (locking, mutual exclusion) operations.
• acquire (s) lock ...
• write (x) ... release (s) unlock ...
• ... acquire (s) lock ... read(x)
• ... release (s) unlock
• Only those fast programs willing to be
  nondeterministic outcome f(processors
  speeds) are not synchronized gt data races
• There are several Relaxed Models for Memory
  Consistency since most parallel programs are
  synchronized characterized by their attitude
  towards RAR, WAR, RAW, WAW to different
  addresses

24
Relaxed Consistency Models The Basics

• Key idea allow most reads and writes to complete
  out of order, but add synchronization operations
  to enforce ordering for critical accesses to
  distinct shared variables, so the partially
  synchronized program behaves as if its processors
  were sequentially consistent
• By relaxing orderings, may obtain performance
  advantages (codes run faster).
• Also specifies range of legal compiler
  optimizations on shared data
• Unless synchronization points are clearly defined
  and programs are synchronized, compiler could not
  interchange read/write pairs for two shared data
  items (AB) because re-ordering
  (rwA,rwBgtrwB,rwA) might affect the results of
  the program
• There are three major sets of (from less to more)
  relaxed orderings
• Relax W?R ordering (gt not all writes completed
  before next read)
• Because it retains ordering among writes, many
  programs that assume sequential consistency
  operate well under this model, without additional
  synchronization. Called processor consistency or
  Total Store Order
• Relax W ? W ordering (not all writes completed
  before next write)
• Relax R ? W and R ? R orders (many models with
  different ordering restrictions rules for
  synchronization to enforce critical ordering)
• Many complexities in relaxed consistency models
  defining precisely what it means for a write to
  complete deciding when each processor can see
  the values that it has written.

25
Observation By Mark Hill

• Instead, can use speculation to avoid long access
  latencies of strict consistency models
• If processor receives an invalidation for a
  memory reference before code involving it is
  committed, the processor uses speculation
  recovery to back out of its computation and
  restart with the invalidated memory reference
  (i.e., fetch the new value and recalculate).
• Aggressive implementation of SC (sequential
  consistency) or PC (processor consist.) has most
  advantages of more relaxed models
• Optimistic SC implementation adds little to the
  hardware costs of a speculative processor
• Speculation allows the programmer to build fast
  codes using the more easily understood, but
  normally slower SC PC models

26
Cross Cutting Issues Performance Measurement of
Parallel Processors

• Performance how well scale as increase Procs
• Speedup fixed as well as scaleup of problem
• Assume benchmark of size np on p processors makes
  sense how scale benchmark to nmp to run on m p
  processors?
• Memory-constrained scaling keeping the amount of
  memory used per processor constant
• Time-constrained scaling keeping total execution
  time, assuming perfect speedup, constant
• Example if 1 hour on 10 P, time O(n3), what if
  100 P?
• Time-constrained scaling 1 hour ? 101/3n ? 2.15n
  scale up
• Memory-constrained scaling 10n size ? 103/10 ?
  100X or 100 hours! 10X processors for 100X
  longer???
• Need to know application well to scale
  iterations, error tolerance

27
Fallacy Amdahls Law does not apply to parallel
computers

• Since some part linear, cannot go above 100X?
• 1987 claim to break it, since 1000X speedup for
  1000p
• researchers scaled the benchmark to have a data
  set size that was 1000 times larger and compared
  the uniprocessor and parallel execution times for
  the scaled benchmark. For this particular
  algorithm the sequential portion of the program
  was constant independent of the size of the
  input, and the rest was fully parallelhence,
  linear speedup with 1000 processors
• True speedup contests (the Gordon Bell prize) do
  not increase the data size as number of
  processors (PUs) increases they also include
  data input times (time to distribute data from
  single disk to all PUs memories).

28
Fallacy Linear speedups are needed to make
multiprocessors cost-effective

• Mark Hill David Wood 1995 study
• Compare costs of SGI uniprocessor and MP systems
• Uniprocessor 38,400 100 MB
• MP 81,600 20,000 P 100 MB
• 1 GB RAM gt Uni 138k vs. MP (181k/P 20k)
  P
• What speedup for better MP cost performance? (if
  Pgt2)
• 8 proc 341k 341k/138k ?2.5X cost, 31 linear
  spup
• 16 proc ? need only 3.6X cost, or 23 linear
  speedup
• Even if need some more memory for MP, memory size
  does not need to increase linearly with P

29
Fallacy Scalability is almost free

• build scalability into a multiprocessor and then
  simply offer the multiprocessor at any point on
  the scale from a small number of processors to a
  large number False, all systems have
  bottlenecks.
• Cray T3E scales to 2048 CPUs vs. 4 CPU Alpha
• At 128 CPUs, it delivers a peak bisection BW of
  38.4 GB/s, or 300 MB/s per CPU (uses Alpha
  microprocessor)
• Compaq Alphaserver ES40 up to 4 CPUs and has 5.6
  GB/s of interconnect BW, or 1400 MB/s per CPU
• Building apps that scale requires significantly
  more attention to load balance, locality,
  potential contention, and serial (or partly
  parallel) portions of program. Speedup of 10X is
  very hard to achieve.

30
Pitfall Not developing SW to take advantage (or
optimize for) multiprocessor architecture

• SGI OS protects the page table data structure
  with a single lock, assuming that page allocation
  is infrequent
• Suppose a program uses a large number of pages
  that are initialized at start-up
• Program parallelized so that multiple processes
  allocate the pages
• But page allocation requires lock of page table
  data structure, so even an OS kernel that allows
  multiple threads will be serialized at
  initialization (even if separate processes)

31
Answers to 1995 Questions about Parallelism

• In the 1995 edition of this text, we concluded
  the chapter with a discussion of two then current
  controversial issues.
• What architecture would very large scale,
  microprocessor-based multiprocessors use?
• What was the role for multiprocessing in the
  future of microprocessor architecture?
• Answer 1. Large scale multiprocessors did not
  become a major and growing market ? clusters of
  single microprocessors or moderate SMPs
• Answer 2. Astonishingly clear. For at least for
  the next 5 years, future MPU performance comes
  from the exploitation of TLP through multicore
  processors vs. exploiting more ILP

32
Cautionary Tale

• Key to success of birth and development of ILP in
  1980s and 1990s was software in the form of
  optimizing compilers that could exploit ILP
• Similarly, successful exploitation of TLP will
  depend as much on the development of suitable
  software systems as it will on the contributions
  of computer architects
• Given the slow progress on parallel software in
  the past 30 years, it is likely that exploiting
  TLP broadly will remain challenging for years to
  come

33
And in Conclusion

• Snooping and Directory Protocols are similar bus
  makes snooping easier because of broadcast
  (snooping ? uniform memory access)
• Directory has extra data structure to keep track
  of state of all cache blocks
• Distributing directory ? scalable shared
  address multiprocessor ? Cache coherent, Non
  uniform memory access
• MPs are highly effective for multiprogrammed
  workloads
• MPs proved effective for CPU-intensive commercial
  workloads, such as OLTP (OnLine Transaction
  Processing, assuming enough I/O to be
  CPU-limited), DSS applications (Data Storage
  Server, where query optimization is critical),
  and large-scale, web searching applications

34
Unused Slides 2009
35
State Transition Diagram for One Cache Block in
Directory Based System

• States identical to snoopy case transactions
  very similar
• Transitions caused by read misses, write misses,
  invalidates, data fetch requests
• Generates read miss write miss message to home
  directory
• Write misses that were broadcast on the bus for
  snooping ? explicit invalidate data fetch
  requests
• Note on a write, a cache block is bigger, so
  need to read the full cache block

36
CPU -Cache State Machine
CPU Read hit

• State machinefor CPU requestsfor each memory
  block
• Invalid state if only in memory or other remote
  cache(s)

Invalidate
Shared (read/only)
Invalid
CPU Read
Send Read Miss message
CPU read miss Send Read Miss
CPU Write Send Write Miss msg to homedirectory
CPU Write Send Write Miss message to home
directory
Fetch/Invalidate Send Data Write Back message to
home directory
Fetch send Data Write Back message to home
directory
CPU read miss gt replace send Data Write Back
message and Read miss to home directory
Exclusive (read/write)
CPU read hit CPU write hit
CPU write miss gt replace send Data Write Back
message and Write Miss to home directory
37
State Transition Diagram for Directory

• Same states structure as the transition diagram
  for an individual cache
• Two actions update of directory state send
  messages to satisfy requests
• Tracks all copies of memory block
• Also indicates an action that updates the sharing
  set, Sharers, as well as sending a message

38
Directory State Machine
Read miss Sharers P send Data Value Reply

• State machinefor Directory requests for each
  memory block
• Uncached stateif in memory

Read miss Sharers P send Data Value Reply
Shared (read only)
Uncached
Write Miss Sharers P send Data Value
Reply msg
Write Miss send Invalidate to Sharers then
Sharers P send Data Value Reply msg
Data Write Back Sharers (Write back block)
Write Miss Sharers P send
Fetch/Invalidate send Data Value Reply msg to
remote cache
Read miss Sharers P send Fetch send Data
Value Reply msg to remote cache (Write back block)
Dirty Exclusive (read/write)
39
Example Directory Protocol

• Message sent to directory causes two actions
• Update the directory
• More messages to satisfy request
• Block is in Uncached state the copy in memory is
  the current value only possible requests for
  that block are
• Read miss requesting processor sent data from
  memory requestor is made only sharing node
  state of block made Shared.
• Write miss requesting processor is sent the
  value becomes the only Sharing node. The block
  is made Exclusive to indicate that the only valid
  copy is in the remote cache. Sharers indicates
  the identity of the owner.
• Block is Shared ? the memory value is up-to-date
• Read miss requesting processor is sent back the
  data from memory requesting processor is added
  to the sharing set.
• Write miss requesting processor is sent the
  value. All processors in the set Sharers are sent
  invalidate messages, and Sharers vector is set to
  identity of requesting processor. The state of
  the block is made Exclusive.

40
Example Directory Protocol

• Block is Exclusive current value of the block is
  held in the cache of the processor identified by
  the set Sharers (the owner) ? three possible
  directory requests
• Read miss owner processor sent data fetch
  message, causing state of block in owners cache
  to transition to Shared and causes owner to send
  data to directory, where it is written to memory
  sent back to requesting processor. Identity of
  requesting processor is added to set Sharers,
  which still contains the identity of the
  processor that was the owner (since it still has
  a readable copy). State is shared.
• Data write-back owner processor is replacing the
  block and hence must write it back, making memory
  copy up-to-date (the home directory essentially
  becomes the owner), the block is now Uncached,
  and the Sharer set is empty.
• Write miss block has a new owner. A message is
  sent to old owner causing the cache to send the
  value of the block to the directory from which it
  is sent to the requesting processor, which
  becomes the new owner. Sharers is set to identity
  of new owner, and state of block is made
  Exclusive.

41
Example
Processor 1
Processor 2
Interconnect
Memory
Directory
P2 Write 20 to A1
A1 and A2 map to the same cache block position
(but different memory block addresses A1 ? A2)
42
Example
Processor 1
Processor 2
Interconnect
Memory
Directory
P2 Write 20 to A1
A1 and A2 map to the same cache block position
(but different memory block addresses A1 ? A2)
43
Example
Processor 1
Processor 2
Interconnect
Memory
Directory
P2 Write 20 to A1
A1 and A2 map to the same cache block position
(but different memory block addresses A1 ? A2)
44
Example
Processor 1
Processor 2
Interconnect
Memory
Directory
A1
A1
P2 Write 20 to A1
Write Back since node(s) with shared cacheblock
cannot pick one cache to send block copy to a
new cache Read-Missing the block, so memory must
send.
A1 and A2 map to the same cache block position
(but different memory block addresses A1 ? A2)
45
Example
Processor 1
Processor 2
Interconnect
Memory
Directory
A1
A1
P2 Write 20 to A1
A1 and A2 map to the same cache block position
(but different memory block addresses A1 ? A2)
46
Example
Processor 1
Processor 2
Interconnect
Memory
Directory
A1
A1
P2 Write 20 to A1
A1 and A2 map to the same cache block position
(but different memory block addresses A1 ? A2)
47
Computers in the News

• Core new microarchitecture last Pentium 4
  (2000)
• Wide Dynamic Execution 4 issue Combine 2
  simple instructions into 1 powerful
  (macrofusion)
• Advanced Digital Media Boost All SSE
  instructions 1 clock cycle
• Smart Memory Access lets one core control the
  whole cache when the other core is idle, and
  governs how the same data can be shared by both
  cores
• Intelligent Power Capability shut down unneeded
  portions of chip
• 80 more performance, 40 less power
• 4 core chips in 2007 (2 copies of dual core?)
• CTO "Intel is taking a conservative approach
  that focuses on single-thread performance. You
  won't see mediocre thread performance just for
  the sake of getting multiple cores on a die.
• CTO urged software companies to support multicore
  designs with software that can efficiently divide
  tasks among multiple execution threads. "It's
  really time to get onboard the multithreaded
  train"