CPE 626 CPU Resources: Adders

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CPE 626 CPU ResourcesAdders Multipliers

• Aleksandar Milenkovic
• E-mail milenka_at_ece.uah.edu
• Web http//www.ece.uah.edu/milenka

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Outline

• Full Adder
• Ripple Carry Adder
• Carry-Look-Ahead Adder
• Manchester Adders
• Carry Select Adder
• Carry Skip Adder
• Conditional Sum Adder
• Hybrid Designs

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Full Adder

• Inputs
• data inputs A, B
• carry in Cin
• Outputs
• sum S
• carry out Cout

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Full Adder
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Full Adder
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Transmission-Gate Adder (1)

• A 1 gt -A 0 gt TG is open gt out -B
• A 0 gt -A 1 gt TG is closed gt out B
• A 1 gt -A 0 gt TG is closed gt out B
• A 0 gt -A 1 gt TG is open gt out -B

TG XOR
TG XNOR
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Transmission-Gate Adder (2)
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Ripple Carry Adder - RCA (1)

• Method 1
• Gi AiBi
• Pi Ai?Bi
• Ci Gi PiCi-1
• Si Pi ? Ci-1
• Method 2
• Gi AiBi
• Pi Ai Bi
• Ci Gi PiCi-1
• Si Ai?Bi?Ci-1

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Ripple Carry Adder - RCA (2)

• Replace AND-OR pair with fast 2-inputs NAND gates

RCA delay is proportional to n and is limited by
the propagation of the carry signal through all
of the stages
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Ripple Carry Adder - RCA (3)
Used in odd stages!
Used in even stages!
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Ripple Carry Adder - RCA (4)

• Carry equations
• Ci1 AiBi PiCiorCi1 (Ai
  Bi)(Pi Ci)Pi NOT(Pi)
• Even stages
• C1i1 PiC3iC4i
• C2i1 Ai Bi
• Ci1 C1iC2i
• Odd stages
• C3i1 PiC1iC2i
• C4i1 AiBi
• Ci1 C3i C4i
• Inputs to stage zeroC30 C40 0

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Carry-Look-Ahead Adder CLA (1)

• Idea speed up carry computation Ci1 Gi
  PiCi
• Propagate Pi Ai Bi
• if Pi 1, then carry from (i-1)th stage is
  propagated
• Generate Gi AiBi
• if Gi 1 there is carry out

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Carry-Look-Ahead Adder CLA (2)
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Carry-Look-Ahead Adder CLA (3)
Domino implementation (Dynamic Carry Gates)
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Carry-Look-Ahead Adder CLA (4)
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Carry-Look-Ahead Adder CLA (5)
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Brent-Kung CLA

• a) lookahead terms
• b) CLG cell
• c) cells can be rearranged into tree
• d) simplified representations for part a)
• e) simplified representation for part c)
• f) lookahead logic for 8-bit adder
• g) Brent-Kung adder

Reduces delay, increases the regularity, reduces
the number of unnecessary switching events (power)
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Manchester Adder Circuits (1)
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Manchester Adder Circuits (2)
Static Stage
Dynamic Stage
MUX stage
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4-bit Manchester Adder
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Carry Bypass
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Carry Select Adder (1)
Compute 2 versions of the addition with
different carry-ins, one assuming that the
carry-in is 0 and another assuming that it is 1
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Carry Select Adder (2)
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Carry Skip Adder Motivation
Computing P3-0 is much simpler than computing
G0-3 Lets compute only P3-0!
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Carry Skip Adder
Practical only if the carry-in signals can be
easily cleared at the start of each operation
e.g. precharging CMOS
Carries begin rippling simultaneously through
each block If any block generates a carry, then
the carry out will be true, even the carry-in may
not be not true yet.
If at the start of each add operation the
carry-in to each block is 0, then correct
carry-outs will be generated carry-out can be
thought of as if it is the G signal
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Carry Skip Adder Analysis

• Assume
• it takes 1 time unit for signal to propagate
  through two logic level
• n bits wide adder
• blocks of size k
• It will take k units for a carry to ripple
  through a block of size k
• Critical path
• k units for the first block
• n/k 2 units to skip the blocks
• k units to ripple through the last block
• Increase the efficiency by varying the blocks
  size
• 20 bits (4, 4, 4, 4, 4,) Delay 4 3 4 11
• 20 bits (2, 5, 6, 5, 2) Delay 9

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Conditional Sum Adder (1)
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Conditional Sum Adder (2)
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Conditional Sum Adder (3)
A 0 0 1 0 1 1 0 1
B 1 0 1 1 0 1 1 0
0 Si0 1 0 0 1 1 0 1 1 0
0 Ci0 0 0 1 0 0 1 0 0 0
0 Si1 0 1 1 0 0 1 0 0 1
0 Ci1 1 0 1 1 1 1 1 1 1
1 Si0 1 0 0 1 0 0 1 1 0
1 Ci0 0 1 1 0 0
1 Si1 1 1 1 0 0 1 0 0 1
1 Ci1 0 1 1 1 1
2 Si0 1 1 0 1 0 0 1 1 0
2 Ci0 0 1
2 Si1 1 1 1 0 0 1 0 0 1
2 Ci1 0 1 1
3 S0 1 1 1 0 0 0 1 1 0
0
S1 1 1 1 0 0 1 0 0 1
0
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Hybrid Designs An Example

• Combine CLA (Carry Look-Ahead) with RCA