TELECOMMUNICATIONS

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TELECOMMUNICATIONS

• Dr. Hugh Blanton
• ENTC 4307/ENTC 5307

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Phase-Locked Loops

• A phase-locked loop (PLL) uses a feedback control
  circuit to allow a voltage-controlled oscillator
  to precisely track the phase of a stable
  reference oscillator, with the important feature
  that the output oscillator can be made to run at
  a multiple of the reference oscillator frequency.

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• Phase-locked loops are used
• as FM demodulators,
• in carrier recovery circuits, and
• as frequency synthesizers for modulation and
  demodulation.
• Phase-locked loops have very good frequency
  accuracy and phase noise characteristics, but
  suffer from the fact that settling times (between
  changes in frequency) can be long.

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• The basic circuit of a phase-locked loop consists
  of
• a reference oscillator,
• a phase detector
• produces an output voltage proportional to the
  difference in phase of the inputs,
• a loop amplifier and filter,
• a voltage-controlled oscillator (VCO), and
• operating at the desired output frequency
• a frequency divider.

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• In operation, the output of the VCO is divided by
  N to match the frequency of the reference
  oscillator.
• The phase detector produces a voltage
  proportional to the difference in phase of these
  two signals, and is used to make small
  corrections in the frequency of the VCO in order
  to align the phase of the VCO with that of the
  reference source.
• The output of the phase-locked loop thus has a
  phase noise characteristic similar to that of the
  reference source, but operates at a higher
  frequency.
• If a programmable frequency divider is used, it
  is possible to synthesize a large number of
  closely spaced frequencies with a relatively
  simple circuit.
• This makes the phase-locked loop very useful for
  commercial wireless applications, especially
  those involving mu ltiple channels.

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• Phase-locked loops can be implemented in either
  digital or analog form, but we will only discuss
  analog PLLs because they are the only type
  capable of operating at RF and microwave
  frequencies.

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• There are several characteristics of phase-locked
  loops that are important in practice.
• The capture range is the range of input frequency
  for which the loop can acquire locking.
• The lock range is the input frequency range over
  which the loop will remain locked
• this is typically larger than the capture range.
• The settling time is the time required for the
  loop to lock on to a new frequency.

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Practical Synthesizer Circuits

• The AMPS cellular system requires a local
  oscillator in the 800 MHz band to receive one of
  several hundred voice channels having 30 kHz
  spacing.
• Using a standard phase locked loop would require
  a reference source operating at 30 kHz and a VCO
  operating near 870 MHz, with a programmable
  divider providing a division ratio of more than
  24,000.
• This would be impractical because of the large
  number of addresses required as well as the high
  frequency at which the divider would have to
  operate.

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• Instead, a phase-locked loop supplemented with a
  mixer and frequency multiplier is used

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• In this synthesizer the VCO operates at the
  frequency fo, which ranges from 217.5 to 222.5
  MHz.
• The VCO output is frequency multiplied by four to
  achieve the desired synthesizer output in the
  range of 870 MHz.
• Part of the VCO output is mixed with a fixed
  reference crystal oscillator at f1 228.02250
  MHz.
• The filtered difference frequency of 6 to 11 MHz
  is low enough to be digitally divided with an
  inexpensive programmable counter.
• The division ratio is selected with a 10-bit
  address to lie between 737 lt N lt 1402, according
  to the desired channel.

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• The output of the divider is compared to a stable
  7.5 kHz oscillator, f2 , and the phase error is
  used to control the VCO.
• When the loop is in lock, the output frequency is
  fout 4(f1 ? f2).
• Thus the output can be stepped in increments of 4
  f2 30 kHz.
• The stability of the output is set by the
  stability of the reference sources f1 and f2.

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• If it is desired to produce an output frequency
  of fout 870.180 MHz. for example, then we solve
  the equation
• 870.180 MHz 4(f1 ? N ? f2)
• 4228.02250 ? N(0.0075)
• This yields N 1397. which is the required
  setting of the programmable divider.

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Phase Detectors

• A phase detector provides an output voltage that
  is dependent on the phase difference between two
  input signals.
• Two input signals of nominally the same frequency
  (wo), but different phases (q1 and q2), are
  applied to the input ports of a 90? hybrid
  coupler.

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• The output voltages developed across the mixer
  diodes can be written as

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• If we assume a square-law response for the mixer
  diodes, and retain only the quadratic terms, the
  diode currents can be written as
• The negative sign of i2 accounts for the reversed
  diode polarity.

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• After combining the diode currents and low-pass
  filtering, the output voltage can be expressed as

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• This result shows that the output voltage of the
  phase detector is proportional to the sine of the
  difference in phase of the two input signals.
• If this difference is small, then the sine
  function can he approximated by its argument, so
  that the phase detector output is proportional to
  the phase difference.
• This is referred to as the linearized phase
  detector model.

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• The constant K, is the phase detector gain
  factor, and accounts for the diode square-law
  constants and current-to-voltage conversion.
• It has dimensions of volts/radian.

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Transfer Function for the Voltage-Controlled
Oscillator

• We can assume that the VCO has an output
  frequency wo that is offset from its free-running
  frequency, wc,by an increment Dw
• where the offset frequency is controlled by the
  control voltage vc applied to the VCO.
• The constant Ko is the VCO gain factor, and has
  dimensions of HZ/V.

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• We define the phase of the offset frequency of
  the VCO as
• Writing frequency as the time derivative of phase
  then gives

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• The integral yields the output phase in terms of
  the control voltage
• The Laplace transform yields

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• Assume a reference input voltage given by
• where qi is the phase of the input waveform.

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• The output voltage of VCO can be written as
• where qo is the phase of the output waveform.
• Note that the output frequency is N times the
  input (reference) frequency, due to the use of
  the frequency divider in the loop feedback path.

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• The phase detector output voltage can be
  expressed in the Laplace transform domain as

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• Since the divider divides the frequency by N, and
  phase is the derivative of frequency, the phase
  will also be divided by N.
• So the relation between the feedback phase qf
  and the output phase, qo, is

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• The control voltage, Vc(s), applied to the VCO is

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• The transfer function is

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• The VCO control voltage is then found as
• The loop phase error is

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• Consider a step change Dw in the frequency, so
  that the input voltage is
• The input phase function is
• where U(t) is the unit step function.

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• The Laplace transform is

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First-Order Loop

• First consider the simplest case of a PLL with no
  loop filter.
• Then H(s) 1, and the VCO control voltage for a
  step change in frequency, reduces to
• due to partial fraction expansion.

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• Since there is a maximum of one pole, the system
  is a first-order loop.
• This result shows how the VCO control voltage
  varies in response to a step change in the input
  frequency.
• At t 0, vc(t) 0.
• The output frequency is w0 wc,the free-running
  VCO frequency.
• In the limit as t??, the control voltage
  exponentially converges to

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• Then the output voltage of the VCO is, after
  locking, given by
• which shows that the output frequency has tracked
  the input step in frequency, and is multiplied by
  N.

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• The time required for the output of the PLL to
  respond to the step change in input frequency is
  called the acquisition time.

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