Design of a 32-Bit Hybrid Prefix-Carry Look-Ahead Adder

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• Design of a 32-Bit Hybrid Prefix-Carry
  Look-Ahead Adder
• By
•  
• Sulabh Vidyarthi

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HYBRID PREFIX-CLA

• GOAL
• To Implement a 32-bit hybrid prefix-carry-look-a
  head adder.
• Implementation style to be used,static and
  dynamic.
• Test the design for Power and speed.

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BACKGROUND

• Parallel Prefix Adders(PPA)
• Carry operator O on (g,p) signal pairs
• where,
• ggpg
• ppp
• Operator O is associative gt
• (g,P) O(g,p)O(g,p)(g,p)O(g,p)O(g
  ,p)

g,p
g,p
O
g,p
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Parallel Prefix Adder(cont)

• Given (p,g) terms for each bit ,they can be
  grouped together to find all the prefixes
  ,which is equivalent to computing all the carries
  in parallel.
• Since operator O is commutative (g,p)s can be
  grouped in any order.
• However ,note that O is not commutative .

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Conventional Prefix Adder(Brent-kung Adder)
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Analysis Of PPAs

• Following highlight the characteristics of a
  general PPA
• Number of O cells
• Tree cell height(delay)
• Tree cell Area
• Cell fan-in and fan-out
• Wiring congestion or wiring length
• Delay path variation(glitching)

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Hybrid Prefix Carry Look-Ahead

• Use of 4-bit Carry-look-ahead blocks to group
  gs and ps.
• Reduces the fan-in and fan-out of any operator
  o block to 2,which in turn reduces input
  capacitance and as a result faster carry
  propagation path.
• The wiring overhead is greatly reduced,which is
  very important at deep sub-micron levels as it
  reduces wiring capacitance and thus low power
  dissipation.
• Balanced Delay path (dont want glitching?).

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HYBRID PREFIX-CLA(cont)
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Analysis of Design

• L1 g,p generation using inputs A and B
• L2Grouping of g and p to generate group carry G
  and P( G0 G4---G28,P0 P4---P28)
• L3Using Operator O on the group G and P to
  generate Gr4 and Pr4
• egGr4G4P4.G0,Pr4P0P4
• L4 Carry generator.eg C4Gr4Pr4.C0
• L5Sum generation using 4-bit carry look-ahead
  generator

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Analysis(cont)

• Delay Analysis
• L1(1T) L2(3T) L3(2T) L4(2T)L5(2T)10T
• The critical path is through L1-L4 One CLA
  Adder unit in L5.
• Tone gate delay

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Tool Flow

• Gate level design of the static and dynamic
  adders verilog(Modelsim)
• Extraction to transistor level (Synopsys and
  Cadence)
• Delay and power analysis Cadence

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Result

• Worst case delay and power estimate

Avg delay Power PDP
Static 1.5ns 2.3mW 2.53E-12
Dynamic 1.1ns 6.5mW 7.15E-12
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Conclusion

• Static and dynamic design both are faster than
  the normal look-ahead adders.
• Easy implementation and simple design using only
  AND,OR and XOR gates .
• Static design has obvious power advantages over
  the dynamic design.The high power dissipation of
  dynamic design outweighs its advantages of high
  speed.
• The Hybrid Prefix CLA has definite speed
  advantage over several other adders.Reduction in
  power dissipation in Domino and Dual rail Domino
  is a potential research area.Techniques such as
  using Mixed-Swing Dual Rail Domino topology can
  give Hybrid Prefix adders and edge over other
  adder types both in terms of speed and Power.
• Mixed-Swing Quad- Rail for Low Power Dual-Rail
  Domino Logic(Bharath Ramasubramanian,L.
  Richard,Herman Schmit)

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References

• 1 R. P. Brent and H. T. Kung, A regular layout
  for parallel adders, IEEE Transactions on
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• 2 P. M. Kogge and H. S. Stone, A Parallel
  Algorithm for the Efficient Solution of a General
  Class of Recurrence Equations, IEEE Transactions
  on Computers, vol. C-22, no. 8, August 1973, pp.
  786-93.
•  
• 3 H. Ling, High-Speed Binary Adder, IBM
  Journal of Research and Development, vol. 25, no.
  2-3, May-June 1981, pp. 156-66.
•  
• 4 V. G. Oklobdzija and E. R. Barnes, On
  implementing addition in VLSI technology,
  Journal of Parallel and Distributed Computing,
  vol. 5, no. 6, December 1988, pp.716-28.
•  
• 5 T. Han, D. A. Carlson, and S. P. Levitan,
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•  
• 6 J. M. Rabaey, Digital Integrated Circuits A
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•  
• 7 Behrooz Parhami, Computer Arithmetic
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