Role of Op-Amps

1
Role of Op-Amps

• widely used building blocks for analog circuits
• widely used in communication circuits
• Widely used in analog signal processing
• critical block for data-converters
• Widely Used in High Volume ICs
• memory read out
• Disk-driver reading-writing

2
New challenges in Analog Design

• Decreased Supply Voltage
• Increased Digital/Analog Interference
• Reduced Testability
• Increased Parametric Variations

3
Critical Specifications for Op-Amps

• High DC Gain

• High Speed/Large Gain-Bandwidth

• Sufficient Output Swing
• High power efficiency

Desirable digital built-in-self-test and
self-calibration
4
Existing structures Limitations
Cascode Amplifier
DC Gain Modest
Speed Excellent
Power Efficiency Good
Frequency Response Good
Output Swing Small
5
Existing structures Limitations
Cascaded Amplifier
DC Gain High
Output Swings Large
Frequency Response Poor
Speed Poor
6
Existing structures Limitations
Positive Feedback Amplifier
DC Gain Large
Speed High
Output Swing Good
Frequency Response Good
Low Yield
7
Our Objective

• Low Voltage Compatible
• High DC Gain
• High Speed
• Good Output Swing
• High Yield
• Standard Digital Process Compatible
• Good Power Efficiency

8
Our Approach

• Find new amplifier architectures
• Rely on digital logic to enhance performance
• Use simple digital circuit sensing amplifier
  performance
• Integrate controllability
• Use adaptive feedback control

9
Positive Feedback Gain-Boosting

• Can operate at very low voltages
• Can achieve very high DC gain
• No compromise in bandwidth
• No appreciable power increase
• Conventional wisdom has two concerns
• positive feedback leads to RHP poles
• gain boosting is limited if requiring robustness
  w.r.t. process variations

10
Our response to the concerns

• positive feedback causes RHP open-loop poles, but
  do not necessarily cause RHP closed-loop poles!
• RHP open-loop poles can actually improve
  performance of closed-loop amplifiers!
• F16/F18 fighter jets have open-loop RHP poles,
  they play critical role in achieving their
  superior closed-loop performance
• no need for robustness across process variations
• use positive feedback pole control after
  fabrication

11
Positive Feedback Operational Amplifiers
Open loop transfer function
Closed-loop transfer function
Open-loop pole
Closed-loop pole
12
Positive Feedback Amplifier Architecture
Exploration

• Some positive feedback amplifier architectures
  have a dc gain that is much more sensitive to the
  feedback control variable than others
• Although architecture optimality may be difficult
  to determine, synthesis techniques may yield
  better structures than those already considered
• Comparative study of several structures with
  existing positive feedback structures

13
Negative Output Conductance Op Amp
Vdd
As (A-1)gdsn ? gds1gds2,
ADC ? 8 !
14
Implementation Block Diagram
First Stage
Negative Conductance Generator
Vi
Vi-
2nd stage
Vip
Vop
Basic Amp
CMFB
Vin
Von
2nd stage
Bias Generator
15
Basic Amplifier and the Second Stage
Second stage
Basic amplifier
16
Negative Conductance Generator
Vdd
M3
M2
M7
M6
Vi
Vi-
Mg1
Mg2
Mn1
Mn2
Vctrl
Vctrl
M1
M5
M4
M8
A
VXX
VXX
Vop
Von
17
Low Gain Stage A
18
Positive Feedback Amplifier Architecture
Exploration
M3
f1(-?1VA-?2VB-?3VOUT)
VB
M4
f2(-?4VA-?5VB-?6VOUT)
VOUT
M2
f3(-?7VA-?8VB-?9VOUT)
VA
M1
VIN
Overhead for realizing this structure can be very
small
19
Example positive feedback amp1
Gain infinity
20
Example positive feedback amp2
Gain infinity
21
Example positive feedback amp3
Gain infinity
22
Example positive feedback amp4
Gain infinity
23
DC Sweep of amp1 in 0.1um process
24
Preliminary Results DBISTSC PFAmp
A Digital Programmable Amplifier
Bifurcation in Positive Feedback Amplifier
Simulation and Measurement Results
25
A digital controllable Amplifier

• Low-Voltage Compatible
• 3 transistors from VDD to VSS
• High Gain
• Attenuator provides positive feedback
• negative-conductance compensation
• High Speed
• Single Stage

26
Small Signal Linear Equivalence
27
Nonlinear Dynamic
Dynamic equation
Equilibrium manifold (DC Transfer)
28
Amplifiers DC Characteristics
y
0
x
?
29
Amplifiers DC Characteristics
y
?0.03
?0
?00.02
L
30
Observations
31
Phase Diagram in Y-? Plane
x0
32
Phase Diagram in Y-? Plane
y
x-0.001
?
33
Phase Diagram in Y-? Plane
y
x0.001
?
34
Observations
35
Pull up/Pull down Circuit
pullup
pulldown
36
Pull up/Pull Down
y
OHOL10
x
37
Pull up/Pull Down
Pull up, stay high
y
OHOL11
Pull down, return high
x
38
Pull up/Pull Down
Pull up, return low
y
OHOL00
Pull down, stay low
x
39
Sensing Process
40
Linear MOS Attenuator
3. ? controlled by Aspect Ratio
4. k controlled by Aspect Ratio
5. Infinite input impedance at DC
41
Adaptively Controllable Attenuator
42
Programmable Attenuation
43
Gain Enhancement Requirement
Gain is related to controllable Attenuator
Required Attenuator Control Code
Achievable Gain Lower Bound
44
Design Specification for Attenuator DAC
1. Sufficient Coverage
2. Fine Resolution
3. DAC Size
45
Effect of Offset on Sensing
offset
O
46
Offset Compensated Sensing Circuit
47
Design Specifications for input DAC
1. Sufficient Coverage
2. Fine Resolution
3. DAC Size
48
Design Specifications
Aspec80dB
y
?0.0001
?0variation0.006
N1?6
Lspec20?V
offset variation 50mV
N2 ?12
49
Combined Sensing and Control Logic

• Implement with inexpensive digital logic
• Time-efficient processing
• Accomplish offset compensation
• Realize optimal control code searching
• Adaptive feedback control

50
Functional Block Diagram
51
Nested attenuation/bifurcation control
initialize
? Attenuator DAC input
?(?L?H)/2
no
bifurcation detection
Bifurcation?
yes
no
?L?
?H?
52
Bifurcation Detection Algorithm
initialize
? Input of offset compensation DAC
2N21 input codes
?(?L?H)/2
no
stepN2?
yes
Pull-up/Down
break without bifurcation
OHOL?
bifurcation detected
00
10
11
? H ?
break
? L ?
53
Convergence Proof
Conditions on offset-DAC range guarantee initial
conditions

• at step 0
• 1.When ??L0, OHOL11
• 2.When ??H2N2, OHOL00
• 3. ?(?L)lt offset ??(?H)
• 4. ?H-?L2N2

54
Convergence Proof (Continue)

• at step k1,
• ?(?L ?H)/2, pull up/down
• if OHOL10, bifurcation is detected, break
• if OHOL11, ?(?)ltoffset, let ?L ?
• if OHOL00, ?(?)?offset, let ?H ?
• if bifurcation is not detected, continue.
• then
• ?(?L)lt offset ??(?H)
• ?H - ?L2N2-(k1)
• At ?L, OHOL11 at ?H ,OHOL00
• This iteration ends either with bifurcation
  detected or stepN2 without bifurcation.

55
Convergence Proof (Continue)

• If stepN2, ?H-?L1
• ?(?L)lt offset ??(?H)
• when ??L, OHOL11, ?(?L)lt lower bound of
  hysteresis
• when ??H, OHOL00, ?(?H)gt up bound of hysteresis
• Lhysgt?(?H)- ?(?L)

?(?L)
?(?H)
offset
potential hysteresis width
Lhys
lower bound
up bound
56
Convergence Proof (Attenuator)
Conditions on m-DAC range guarantee initial
conditions

• at step 0
• 1.When ? ?L0, no bifurcation
• 2.When ? ?H2N1, bifurcation
• 3. ?(?L)??0lt ?(?H)
• 4. ?H- ?L2N1

57
Convergence Proof (Attenuator)

• step k1 ?(?L)??0lt ?(?H), ?H- ?L2N2-k
• let ?(?L ?H)/2, do bifurcation detection
• if bifurcation is detected, ?(?)gt ?0 ,let ?H ?
• else let ?L ?
• at both situations, ?(?L)??0lt ?(?H), ?H-
  ?L2N1-k-1

58
Convergence Proof (Attenuator)

• This iteration ends with no bifurcation and finds
  an optimal control code ?L

• Aachieved ? Aspec

59
Simulation Environment

• Ami 0.5um CMOS (most)
• Cadence
• Spectre (simulator)
• Hspice (simulator)
• SpectreVerilog (simulator)
• Analog Artist
• Schematic
• Virtuoso (layout tool)
• SEDSM (Floor-plan /Route )
• Synopsys

60
Simulation Results
16-b R-1.8R DAC
??5?VltLspec
Offset Compensation DAC Characteristics
61
M2
M4
M6
M1
M3
M5
62
Digitally controlled PF Amplifier
VDD
?
?

-

-
cmfb
VSS
63
Two Stage Amplifier
?
vo1
vi1
vop
PU
PD
A2
Amp
A1
vo2
vi2
von
64
R-2R DAC
Matched 2R
-
R
Matched 2R
-
R
Designed 2R
-
xR
Designed 2R
-
xR
For K LSB
For K LSB
For N
-
K MSB
For N
-
K MSB
output
R
R
R
R
0.94R
0.94R
2R
1.9R
2R
1.9R
2R
2R
2R
2R
2R
2R
2R
2R
R-2R
0
1
N
-
2
N
-
1
0
1
N
-
2
N
-
1
DAC
ground
ground
reference
reference
Xlt1
Xlt1
LSB
LSB
MSB
MSB
65
Two way switch
VH
Vo
Vo
0
0
VL
VH
VL
66
Comparator
Vout
Comparator
67
Self-Calibrated High Gain Amplifier
16-bit R-2R
DAC
code
RN
calibr
vcm
controller
Amp
Comparator
CLK
PU
PD
DS
68
Algorithm for Controller

• Step 1 Initialize ?
• Step 2 Sweep input
• Step 3 Use pull-up/down method to detect
  hysteresis
• Step 4 if hysteresis exists, decrease ? else
  increase ?
• Step 5 if ? is very close to ?0, finish else
  goto step 2

69
Searching Process
Offset Compensation DAC
32768
16384
24576
16384
28672
25578
24577
No Bifurcation
Attenuator Control DAC
Max searching time 7x16 cycles
70
Bifurcation Simulation
x0
71
Pull-up/Pull Down
x-0.1mV
72
AC Response
50dB gain enhancement
73
Step Response
74
Step Response
Significant Settling accuracy Improvement
75
Robustness Over Temperature
76
Simulated Performance in 90nm CMOS
Easy Migration
77
One Fabricated Amplifiers Performance
Tab. 1 Simulated DC gain over wide temperature
range
Gain (dB) SS SF FS FF NN
0C 84 85 72 92 103
27C 82.2 89 84 85 110
80C 70.4 84.5 83.7 89 88
manual tuning
AMI 0.5um CMOS
Tab. 2 Measured DC gain of fabricated chips
Chip 1 2 3 4 5
Gain (dB) 90 87.6 89.3 84.5 86.5
78
Two-Stage to enhance linearity
79
Two stage amp DC Sweep
80
Two stage Gain vs Vout
gt130dB over - 0.75V
81
Amplifier performance summary

• Berkeley projected 90nm process
• power supply voltage Vdd1.1
• two stage total current Itot18ma
• Total power consumption Ptot20mw
• Capacitive load CL4p
• Unity gain frequency UGF 1.35GHz
• Phase margin at UGF 39 deg
• Frequency at gain 2 G2F 804MHz
• Phase margin at G2F 65 deg

82
Switched-Capacitor Amplifier
Precision Multiply-by-Two Circuit
83
Transient Simulation Results
100 MS/s 60 swing ?0.3Vdiff Settling accuracy
8.9e-4 10.1 bits
84
Transient Simulation Results
100 MS/s full swing ?0.5Vdiff Settling accuracy
0.0013 9.6 bits
85
Transient Simulation Results
80 MS/s 60 swing ?0.3Vdiff Settling accuracy 2
.1e-4 12.24 bits
86
Transient Simulation Results
40 MS/s Settling accuracy 3.1e-5/0.56.2e-5 14.
0 bits
input0.25V output0.499969V
87
Transient Simulation Results
10 MS/s Settling accuracy 6e-6/0.51.2e-5 16.3
bits
input0.25V output0.499994V