Dynamically Reconfigurable Bio-inspired Hardware - PhD Thesis -

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Dynamically Reconfigurable Bio-inspired
Hardware- PhD Thesis -

• Andres Upegui
• Reconfigurable Digital Systems Group RDSG
• Ecole Polytechnique Federale de Lausanne - EPFL

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Introduction
Dynamically reconfigurable bio-inspired hardware
Dynamic reconfigurable computing
Bio-inspired systems
The goal of this thesis is to propose
methodologies and architectures for implementing
bio-inspired hardware systems by partially
reconfiguring current commercial reconfigurable
computing devices
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Why Bio-inspiration?

• Adaptability learning and evolution.
• Robustness self-reparation and self-replication.
• Autonomy No external modifications are required
  during organisms development.

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Reconfigurable Computing
Dynamic Reconfigurable Computing
Microprocessors
Software
flexibility
FPGAs
Reconfigurable Computing
ASICs
Static
Hardware
performance
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Field Programmable Gate Arrays FPGAs
programmable functions
programmable interconnections
configuration
I/O cell
logic cell
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AnalogyProgrammable logic Living beings
Genotype
Genotype
0010101110101101010111
Phenotype
Phenotype
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Evolvable Hardware The Beginning
In Adrian Thompson. An evolved circuit,
intrinsic in silicon, entwined with physics. In
Evolvable Systems From Biology to Hardware,
LNCS, volume 1259, pages 390405.
Springer-Verlag, 1997.
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Dynamic Partial Reconfiguration
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Dynamic Partial Reconfiguration

• Mainly supported by two FPGA vendors
• Xilinx
• Atmel
• Virtex II dynamic reconfiguration design flows
• Module based
• Difference based
• Direct bitstream manipulation

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Module based flow
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Difference based flow
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Direct Bitstream Manipulation

• Directly generate a bitstream, without using
  vendors tools.
• An on-chip processor can generate and modify the
  device configuration.

On-chip bitstream generator
001011101011101010
001101101011101010
Internal Configuration Access Port - ICAP
A. Upegui and E. Sanchez. Evolving hardware by
dynamically reconfiguring Xilinx FPGAs. In
Evolvable Systems From Biology to Hardware,
LNCS, volume 3637, pages 5665, 2005.
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Issues when Evolving Virtex-II FPGAs

• Huge search space
• A XC6200 logic cell 18 configuration bits
• A Virtex-II CLB 880 configuration bits
• Risk of internal contentions
• XC6200 interconnections based on multiplexers
• Virtex-II interconnections based on switch
  matrices
• Configuration bitstream format
• XC6200 fully documented
• Virtex-II not documented

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Solutions

• Two typical approaches
• Custom bio-inspired circuit efficient and
  flexible
• Virtual reconfigurable circuit fast setup
• In this thesis
• Real dynamic partial reconfiguration of
  commercial devices efficient and affordable.
• Three techniques for evolving systems by using
  each one of the DPR design flows.

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Modular Reconfiguration Topology Evolution of
Artificial Neural Networks
Different possible configurations for module n
FPGA
Module 1
Module 2
Module n
PC running an EA
A. Upegui, C. A. Peña-Reyes, and E. Sanchez. An
FPGA platform for on-line topology exploration of
spiking neural networks. Microprocessors and
Microsystems, 29(5)211 223, 2005. A. Upegui,
C. A. Peña-Reyes, and E. Sanchez. A methodology
for evolving spiking neural-network topologies on
line using partial dynamic reconfiguration. In
ICCI - International Conference on Computational
Intelligence, Medellin, Colombia, 2003.
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Hardware-oriented Spiking Neuron Model
Membrane potential
A. Upegui, C. A. Pena-Reyes, and E. Sanchez. A
functional spiking neuron hardware oriented
model. In Computational Methods in Neural
Modeling I, LNCS, volume 2686, pages 136143.
Springer-Verlag, 2003.
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On-chip Hebbian Learning
Synthesis of learning neurons. Spartan-II XC2S200 Synthesis of learning neurons. Spartan-II XC2S200
30-input neurons Full network (30 30-input neurons)
53 slices 1500 slices
2.25 63.78
A Virtex-II XC8000 can contain up to 2000 of
these neurons
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Frequency Discrimination with On-chip Hebbian
Learning
A. Upegui, C. A. Pena-Reyes, and E. Sanchez. A
hardware implementation of a network of
functional spiking neurons with Hebbian learning.
In Biologically Inspired Approaches to Advanced
Information Technology, LNCS, volume 3141, pages
233243. Springer-Verlag, 2004.
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Difference Based Reconfiguration
Coevolutionary Fuzzy Systems

• Fuzzy systems inspire from human reasoning
• Unlike other bio-inspired techniques, fuzzy
  systems provide interpretability.
• Adaptation can be done by means of EAs, in this
  thesis by a coevolutionary approach Fuzzy CoCo.

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Coevolutionary Fuzzy Platform
AND
OR
0001011101011010
0101111011001001
GA
OR
FPGA Editor
OR
AND
OR
Bitgen
G. Mermoud, A. Upegui, C. A. Pena, and E.
Sanchez. A dynamically-reconfigurable FPGA
platform for evolving fuzzy systems. In
Computational Intelligence and Bioinspired
Systems, LNCS, volume 3512, pages 572581.
Springer-Verlag, 2005.
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Fuzzy Rule Hard Macro
a
b
gt
a
b
MUX
Fuzzy OR MAX
Fuzzy AND MIN
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Direct Bitstream Manipulation Cellular
Automata

• Array of computing cells, each implementing a
  state and an update rule.
• Non-uniform CA implement diverse update rules
  along the array.
• EAs have been used to determine these rules.
• In this thesis one dimensional cellular automata
  evolved with cellular programming.

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Cellular Automata Hard-macro
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Self-Reconfigurable Platform
Rule determination of non-uniform CA with
cellular programming
00110101
11110101
A. Upegui and E. Sanchez. On-chip and on-line
self-reconfigurable adaptable platform the
non-uniform cellular automata case. Proceedings
of the 20th IEEE International Parallel and
Distributed Processing Symposium (IPDPS06), page
206, 2006.
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Direct Bitstream Manipulation Random
Boolean Networks

• The same automaton than CA but supporting an
  arbitrary connectivity.
• Very related to randomly connected neural
  networks.
• Flexible connectivity is very expensive in terms
  of hardware resources (more than 80 of FPGA area
  is used in switch matrices).

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RBN Cell Rules and InterconnectionsImplementatio
n
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RBN Hard Macro in a Virtex-II CLB
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Self-Reconfigurable System for Randomly
Connecting Systems
1101101010011 0010101001010 0101010101010
0011000110010
0011010111001 0011010101010 0101100101100
1010101111111
11110000
11010111
00
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A. Upegui and E. Sanchez. Evolving hardware with
self-reconfigurable connectivity in Xilinx FPGAs.
In Proceedings of the 1st NASA /ESA Conference on
Adaptive Hardware and Systems(AHS-2006), pages
153160, Los Alamitos, CA, USA, 2006.
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Case Study 1 YaMoR

• YaMoR
• Yet another Modular Robot

R. Moeckel, C. Jaquier, K. Drapel, E. Dittrich,
A. Upegui, and A. Ijspeert. YaMoR and bluemove -
an autonomous modular robot with Bluetooth
interface for exploring adaptive locomotion. In
Proceedings CLAWAR05, pages 685692, 2005. R.
Moeckel, C. Jaquier, K. Drapel, E. Dittrich, A.
Upegui, and A.J. Ijspeert. Exploring adaptive
locomotion with YaMoR, a novel autonomous modular
robot with Bluetooth interface. Industrial Robot,
33(4)285290, 2006.
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Some Initial Configurations with YaMoR
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But, Wires Must be Removed!!
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YaMoR Electronic Boards

• Bluetooth Board
• Bluetooth-ARM System on Chip (SoC)
• 16 MBit Flash memory.

• FPGA board
• Spartan-3 XC3S400 FPGA with 400.000 gates
• 4 MBit high speed SRAM.

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Reconfigurable Controller
A. Upegui, R.Moeckel, E. Dittrich, A. Ijspeert,
and E. Sanchez. An FPGA dynamically
reconfigurable framework for modular robotics.
ARCS05, System Aspects in Organic and Pervasive
Computing, Workshop Proceedings, pages 8389,
2005.
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Case Study 2 ROPES

• ROPES Reconfigurable Object for Pervasive Systems

Ethernet
32 MB SDRAM 2 MB SRAM
Partial reconfiguration layout oriented
uClinux
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Self-Reconfigurable System in ROPES
10010111010101
Ethernet or Bluetooth
Reconfigurable cryptographic coprocessor
MicroBlaze Soft-processor
ID
On-board SRAM
10010111010101
ID
ICAP
Bus macros
A. Lagger, A. Upegui, E. Sanchez, and I.
Gonzalez. Self-reconfigurable pervasive platform
for cryptographic application. In Proceedings of
the 16th International Conference on Field
Programmable Logic and Applications, Madrid,
Spain, 2006.
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A Practical Application Channel Equalization
Particle Swarm Optimization with Discrete
Recombination - PSODR
Binary Radial Basis Function - BRBF
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The Equalizer in Hardware
J. Peña, A. Upegui, and E. Sanchez. Particle
swarm optimization with discrete recombination
An online optimizer for evolvable hardware. In
Proceedings of the 1st NASA /ESA Conference on
Adaptive Hardware and Systems(AHS-2006), pages
163 170, 2006.
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Conclusions

• I have presented a general framework for evolving
  hardware by partially reconfiguring Xilinx FPGAs.
• Three techniques for explioting partial
  reconfigurability when evolving hardware
  module-based, difference-based, and direct
  bitstream manipulation.
• A new design flow for partially reconfigurable
  systems in Xilinx FPGAs, presenting several
  advantages over the existing design flows
• The generated bitstream is not dependant on
  Xilinx design tools.
• The configuration bitstream can be generated
  on-line and on-chip with a low-cost processor.
• Thanks to the low-level specification, the
  bitstream generation takes considerably less time
  than conventional design flows.

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Conclusions

• A compact and performant architecture for a
  spiking neuron model with hebbian learning, and
  the characterization of the computational power
  of a network of them.
• A hardware implementation of the coevolutionary
  fuzzy system design technique Fuzzy Coco, where
  each one of the evolved species is independently
  reconfigured.
• A reconfigurable matrix array supporting random
  topological configurations, useful for digital
  hardware implementations of randomly connected
  networks, such as random boolean networks, echo
  state machines, liquid state machines, or for
  evolving networks with arbitrary connectionism.

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Conclusions

• During this thesis I co-supervised the design of
  a new modular robot platform YaMoR whose most
  distinctive feature is the inclusion of an FPGA
  board and a Bluetooth board in each module.
• A framework for implementing partially
  reconfigurable controllers on the YaMoR platform.
• During this thesis I co-supervised the design of
  a prototyping platform for reconfigurable
  pervasive systems, along with a system setup for
  implementing a reconfigurable cryptographic
  coprocessor.
• A new hardware-oriented PSO algorithm, which
  performs better than conventional PSO, and whose
  utilization has been tested in a channel
  equalization task.

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1101101010011
0011010111001