EEL 3705 3705L Digital Logic Design

1
EEL 3705 / 3705LDigital Logic Design

• Fall 2006Instructor Dr. Michael FrankModule
  99 (Extra Slides) Design Examples

2
MAX 7000 Programming Example

• Demonstration of the Design and Programming of an
  Extremely Simple Example Circuit for the MAX 7000
  PLD in Quartus

3
MAX Package Pin Assignments
From MAX 7000 PLDFamily Datasheet (p.61)
4
That tells us what the package pins areNow,
what about the plug headers?
5
Mapping from header holes to package pins

• From page 7 in the UP2 User Guide.

6
MAX UP2 Header Pin Assignments
See UP2 User Guide, p. 7, table 3. 7-segment
display pins in green taken from p.9, table 4
P2
VCCINT
GCLK1
GLCRn
GND
dot2
VCCIO
d2
13
12
g2
74
X
f2
P1
TDI
c2
15
14
GND
72
73
11
9
7
5
3
1
83
81
79
77
75
TDO
b2
17
16
70
71
X
10
8
6
4
2
84
82
80
78
76
GND
a2
dot1
19
18
68
69
e2
OE1
OE2
GND
g1
VCCIO
21
20
VCCIO
66
67
TMS
e1
f1
23
22
64
65
VCCIO
TCK
25
24
d1
62
63
GND
VCCIO
c1
27
26
b1
60
61
34
36
38
40
42
44
46
48
50
52
X
GND
a1
29
28
58
59
33
35
37
39
41
43
45
47
49
51
53
31
30
56
57
P3
GND
X
32
GND
54
55
VCCIO
VCCINT
P4
Color key
Available
Power
Ground
Not Attached
Assigned
7
Seven-Segment Display Example

• Want to display HI. on the 7-seg display.

Active-low LED controllow on, high
off. Unused output pins aretied to GND by
default. So, LEDs are on by default. Can display
HI. byturning off a1, d1, dot1,a2, b2, c2,
d2, g2. Connect these pins to Vcc. Leave others
alone.
a1
a2
b1
f1
b2
f2
g1
g2
c1
e1
c2
e2
d1
dot1
d2
dot2
8
Schematic for HI. example
9
Pin Assignment in Quartus
10
Photo Showing Proper Function
11
FLEX 10K VGA Graphics Programming Examples

• A Simple VGA Driver, Test PatternGenerator, and
  Character Generator for the FLEX 10K

12
VGA Cable Pinouts
(p.13)
13
Video Scan Line Timing

• fclk 25.175 MHz tclk 39.722 ns

(p. 26)
782 tclk
142 tclk
95 tclk
806 tclk
640 tclk 25.42 µs
95 tclk
48 tclk
32.02 µs 806 tclk
24 tclk
14
Scan Line Timing Hardware
15
Video Frame Timing

• trow 32.022 µs

514 rows
(p. 27)
34 rows
11 rows
32 rows
2 rows
525 rows
16.8 ms
15.37 ms
16
Frame Timing Hardware
17
Entire VGA Driver Schematic
18
Example Test Circuit for VGA Driver

• Goal Generate diagonal color test pattern
• Computed by formula RGB2..0 (row col)6..4

19
Photo of VGA CRT Monitor Screen

• Circuit works perfectly!
• Files are in VGA_example.zip on BB

20
VGA Text DisplayProgramming Examples

• Character Generator and Text Page Display for
  the FLEX 10K

21
Goal of Next Example Make the FLEXDisplay my
ASCII Table!
22
VGA_char Initial circuit for testing ability to
display text characters

• Uses the same VGA_driver module.
• Down-samples to 320240 resolution.
• Fills display w. an 8024 array of null symbols
  Ø .
• Each glyph rendered as 610 fat (22) pixels.
• White text on black background.

23
Design Entry of Text Character Font

• Hand-draw each character glyph as a 68 block of
  pixels within an 810 pixel character space.

NUL_glyph.mif file
DEPTH 8 WIDTH 6 ADDRESS_RADIX
HEX DATA_RADIX BIN CONTENT BEGIN 0
001101 1 010010 2 100101 3 101001 4
010010 5 101100 6 000000 7 000000 END

• Encode pixel bits in a .mif file used to
  initialize a ROM module for the font data.

descenderarea
verticalspacing
24
Output of VGA_char Example
25
Design for a complete 128-character ASCII font
including color glyphs for control pictures
26
Display circuit for 128-character color font
ASCII table
Uses a 1,0246 bitfont pixel ROM anda 1283 bit
(rgb) font color ROM.
Note We set the first two columns of each
character (rather than the last 2) to be 0. This
gives an extra 2 clock cycles of breathing room
while the character pixel/color information is
being fetched from ROM.
27
Successful Color Font Display(VGA_font_color
project)
ASCII Tablerepeatsacross screen
28
Close-Up Photo of One ASCII Table
29
Next example Display a screenful of arbitrary
text

• For example, here is a screen design mocked up as
  a table in MS Word ?

30
Use SciTE and HexEdit to create an ASCII text
file containing the raw character data
DEL character
31
Write a short C program to convert the raw text
data to MIF file format
32
Modify logic design to fetch the character codes
to display from a ROM
33
Screenshot showing successful display of the
custom 4024-character page of text
Feature idea for next versionprovide the
option not to explicitly draw all of
thenormally non-printing characters,
especially SP (?)...Activate the suppress_space
option with a pushbutton
34
Ideas for Further Work

• Use the ROM to initialize a RAM with modifiable
  character data.
• Make display of control characters a selectable
  option
• Create a PS/2 keyboard decoder
• Implement a simple word-processing application
• Develop a simple machine language interpreter for
  a character-encoded instruction set.
• Then program some simple video games based on the
  text display!
• Also create some videogames in pure logic based
  on more direct use of the VGA driver (pong, etc.)

35
Ping-Pong VideogameExample

• Dynamic Display Generation, Layered Graphics,
  Controlled Paddle Motion

36
Real-World Ping-Pong Table
Image credit Wikipedia
37
Ping-Pong Game Display
Mocked-up here as a Powerpoint animation
Ball
Leftpaddle
Rightpaddle
Midline
Net
38
Plan for Game Controls

• Left pushbutton FLEX_PB1 will control left
  players paddle
• Held down move down, released move up
• Right button controls right paddle similarly

39
Plan for games physics

• When the ball hits a wall, it bounces elastically
• Horizontal or vertical velocity will change sign
• When the ball hits a paddle
• Its vertical velocity (vy) will increase or
  decrease depending on which direction paddle is
  moving
• Paddle moving up ? vertical velocity decreases
• Paddle moving down ? vertical velocity increases
• Its horizontal velocity (vx) will change sign
  (bounce)
• Its absolute value will increase if the ball hits
  near the center of the paddle (a good hit)
• Its absolute value will decrease if the ball hits
  near the edge of the paddle (a glancing blow)

40
Prioritized Color Layer Combiner

• Allows one graphics object to override another

41
Table Surface Stipple Color Layer Generator

• Pure green makes for an overly bright table
  surface, so instead we use an XOR gate to create
  a green-on-black checkerboard stipple pattern

implementedby this circuit
42
Game Display Generator (top half)

• Note we use two instances of the color_mixer
  module to combine the outputs of the table,
  midline, and net renderers

43
Paddle Renderer (only left paddle so far)

• Left paddle is rendered as a 1050 pixel blue
  rectangle starting at y coordinate lpy (input)

44
Entire Ping-Pong Display Renderer (so far)
Altogether were using three of our color_mixer
modules in order to correctly combine the
graphics on the playing surface, midline, net,
and paddle layers.
(default black background)
green stipple
Increasinggraphics layerpriority
white midline
black net
blue paddle
45
Left Paddle Controller Circuit
Comparatorallows paddley to be updated iff its
new value is in the range 0,480-50 0,430
Adder increments/decrements paddley coordinate
indirection determinedby pushbutton 1
46
Top-Level Circuit for Ping-Pong Game (so far)
47
Demonstration of Game Display (so far)

• We can hook up the board directly to the lecture
  hall video projector in order to demonstrate the
  left paddles live functionality to the class

48
Ping-Pong Ball Sprite Design
Planning the bitmap
Approx. on-screenappearance
DEPTH 10 WIDTH 10 ADDRESS_RADIX
HEX DATA_RADIX BIN CONTENT BEGIN 0
0001111000 1 0111111110 2 0111111110 3
1111111111 4 1111111111 5 1111111111 6
1111111111 7 0111111110 8 0111111110 9
0001111000 END
ball_sprite.mif
49
Still to do on ping-pong game

• You might like to try some of these yourself!
• Add 2nd, red paddle on right, controlled by PB2
• Create a ball object, implement game physics
• Adjust movement speeds for best playability
• Add a scoreboard using the 7-segment display
• Hook up an external speaker to the expansion bus
• and generate beep sounds when the ball bounces
  off a wall or a paddle or goes out of bounds

50
Keyboard and Mouse Input Using the PS/2 Port
51
PS/2 Port Pins

• From UP2 Users Guide, p.13

52
Verifying the On-Board Port Circuitry

• We check the UP2 board schematics and see that
  there is no port-driving circuitry between the
  PS/2 port and the FLEX chip
• The pullup resistors for the open-drain output
  drivers must be implemented internally within the
  FLEX chip

UP2 board schematics, page 6
UP2 board schematics, page 1