Let's Put it Together

1
Lecture 15

• Let's Put it Together!
• A Manual Processor (part 2)

2
The Basic Processor Architecture from last
lecture was
IR7
Data In
8
8
SelA
F-ALU
F-Shifter
A
8
8
Res
8
B
Data
Out
ALU
SelC
CY-in
1
Carry Out
CY-out

3
Registers A B and Res are all of the form
Register C is a single D-Q flip-flop
4
Multiplexer to select A has the form
The multiplexer to select C is a single bit
version of this
5
The Arithmetic and Logic Unit
6
The Shifter (A special multiplexer)
7
We now need to make it work!
IR7
IR0
Data In
8
8
IR7
IR6 IR5 IR4
select
select
A
MPX
IR3 IR2 IR1
select
8
8
SHIFTER
Res
8
B
Data
Out
ALU
CLKRES
IR0
CY-out
Carry Out
select
1
CY-in
MPX
8
Instruction Format 1
Instruction Register R

• The multiplexers are controlled by bits 0 and 7
  of the instruction
• SELA 0-1 Selects the input to the A register
• 0 selects shifter output, 1 selects external
  Data Input.
• SELCY 0-1 Selects the input to the CARRY-in of
  the ALU
• 0 selects logic 1, 1 selects C-out

9
Instruction Format 2
Instruction Register IR

• SELALU bits 4, 5 and 6 selects the ALU output
• 000 ZERO 001 B-mi-A
• 010 A-mi-B 011 A-pl-B
• 100 A-xor-B 101 A-or-B
• 110 A-and-B 111 MINUSONE

10
Instruction Format 3
Instruction Register IR

• SELSHIFT 0-7 Selects the shift function
• 000 Unchanged 001 Arithmetic Left Shift
  
• 010 Unused 011 Logical right
  shift
• 100 Unchanged 101 Left shift with carry
• 110 Arithmetic right shift 111 Right shift
  with carry

11
Execution Cycle of the Manual Processor

• 1. Load the "Data In" lines into the IR
  register.
• The first instruction (op-code)
• 2. Load the A register (from Data In or Shifter)
• 3. Load the B and the C registers
• 4. Load the "Data In" lines into the IR register
  The second instruction (op-code)
• 5. Load the RES and the C registers
• .... Go back to step 1 ....

12
The State Transition Diagram
Input 1OPERATE, 0IDLE
State 2
State 1
0,1
out
0,1
out
Initial state
CLKA
CLKIR
State 3
out
1
CLKB
CLKC
State 0
0,1
idle
no output
State 4
out
1
0
0
0,1
CLKIR
State 5
out
CLKRES
CLKC
13
The State Transition Diagram
Input 1OPERATE, 0IDLE
As an alternative we could force the processor
into the idle state as soon as the input goes to 0
14
The Program

• The execution cycle implicitly defines the format
  of the program.
• At each step a new item arrives on the data in
  lines synchronised with the system clock.

15
The State and Clock Controller
CLKIR
OPERATE
CLKA
CONTROL
CLKB
System Clock
CLKRES
CLKC
16
The Processor execution cycle
ClkIR
ClkIR
ClkA
17
The State Transition Table
OPERATE/IDLE Current State
Flip-flops Next State D2 D1 D0
0
0 0 0 0
0 0 0 0
0
1 0 0 1
0 0 0 0
0
2 1 0 0
0 0 0 0
0
3 0 1 0
0 0 0 0
0
4 1 0 1
0 0 0 0
0
5 1 1 0
0 0 0 0
0
6 0 1 1
? X X X
0
7 1 1 1
? X X X


1
0 0 0 0
1 0 0 1
1
1 0 0 1
2 1 0 0
1
2 1 0 0
3 0 1 0
1
3 0 1 0
4 1 0 1
1
4 1 0 1
5 1 1 0
1
5 1 1 0
1 0 0 1
1
6 0 1 1
? X X X
1
7 1 1 1
? X X X
18
Karnaugh Maps of the Controller
19
Checking the Unused States
OPERATE/IDLE Current State Flip-flops
Next State D2 D1 D0




0 6
011 0
0 0 0
0 7
111 0
0 0 0




1 6
011 2
1 0 0
1 7
111 4
1 0 1

• Thus, if the OPERATE/IDLE signal is at logical 0
  the system drops into the IDLE state immediately
  and the processor is ready to start working
  properly.

20
Control Signals (output logic)
Flip-Flop Outputs State
Required Clock Output

000 0 none
001 1 CLKIR
100 2 CLKA
010 3 CLKC , CLKB
101 4 CLKIR
110 5 CLKC, CLKRES
Q1,Q0
Q1,Q0
Q1,Q0
Q2
Q2
Q2
00 01 11 10
00 01 11 10
00 01 11 10


0 0 X 0
0
0 0 X 1
0 0 X 1
0
0







1 0 X 0
1
0 0 X 0
0 0 X 1
1
1
CLKC Q1
CLKA Q2Q1'Q0'
CLKB Q2'Q1
Q1,Q0
Q1,Q0
Q2
Q2
00 01 11 10
00 01 11 10


0 1 X 0
0 0 X 0
0
0




0 1 X 0
1
0 0 X 1
1
CLKIR Q0
CLKRES Q2Q1
21
Gating the Registers

• The controller generates outputs for ClkA, ClkB,
  ClkC, ClkIR and ClkRes.
• These signals are positive throughout the state,
  they are used as follows

For safe design the controller changes on the
negative edge of the clock and the registers on
the positive edge
22
Program Execution Decrement a Number

• 1. Set OPERATE/IDLE signal to 0 apply two
  clocks.

Processor in IDLE state
2. Set OPERATE/IDLE to 1 apply one clock pulse.
Processor now waiting for first instruction data.
3. Set input data to 11110000 apply one clock
pulse.
Code is in the IR register. ALU is 11111111 (
-1), shifter unchanged.
Because IRX1 the ALU output is clocked into the
A register it is now -1.
4. Apply one clock pulse
23
Program Execution Decrement a Number

• 5. Set input data to dddddddd the number you
  want to decrement

Number is clocked now into the B register. 0 is
clocked into the B register.
Code is in the IR register. The ALU is set to A
plus B and the shifter to unchanged
6. Set input data to 00110000 and apply one clock
pulse.
7. Apply one clock pulse.
The result "B plus (-1) is clocked into the RES
register, the C bit indicates overflow
24
The Decrement instruction in a program

• The decrement instruction could be used as part
  of a longer program.
• The result of decrementing the number goes back
  to memory via the data out lines

25
At last

• We have succeeded in executing one program
  instruction!
• Well take a look at getting the instructions in
  and the results out next time.