V124S Trigger Module

1
V124S Trigger Module

• Heather Hartmann (BNL)
• SNS Global Controls

2
Features

• Decoding of Event System Codes
• Extraction of Revolution Clock from carrier
• 8 identical, independent or cascadable trigger
  channels
• Buffered Phase Delay Revolution Clock
• External Trigger Inputs for cascading modules

3
Inputs/Outputs

• Inputs
• 16.92 MHz SNS encoded event clock
• Differential PECL
• 4 Trigger Channels
• Single ended TTL - 50 ohm
• Outputs
• 1.05 MHz RF Ring clock (Frev) with adjustable
  phase delay
• Differential PECL
• 8 Trigger Channels
• Single ended TTL 50 ohm drivers
• Chassis ground shield

4
Block Diagram Typical Channel
Encoded Events
Clock 16.92 Mhz
Event Link Recovery and Phase Locked Loop
REV CLK Out
1.05 MHz REV CLK
? 16 RESET
Phase Delay
Serial NRZ Data
33.84 MHz
Event Decoder
Tzero
clk
PULSE WIDTH COUNTER en
Event
8
Output
Event Mask RAM Look Up Table
clk SUBREVOLUTION en
COUNTER tc reload
clk REVOLUTION tc en
COUNTER reload
CLK FINE DELAY EN
External
VMEbus
Next Chan Sub-Revolution Counter
To Next Chan Revolution Counter
No Halt
clk TRIGGER COUNTER en
tc
reload
S R
5
Channel Counters

• Revolution (16 bits)
• Enabled by
• an Event (configurable)
• an External Trigger
• a VMEbus Command
• Previous Channel Fine Delay Enable
• Decrements on occurrence of Frev
• Maximum Delay 62ms _at_1GeV

6
Channel Counters (contd)

• Sub-revolution (8 bits)
• Enabled by
• An Event (configurable)
• A VMEbus Command
• Revolution Counter Terminal Count
• Decrements on the occurrence of 32 Frev
• (Frev 945.4ns _at_ 1GeV)

7
Channel Counters (contd)

• Trigger (32 bits)
• Enabled by Sub-revolution Counter Enable
• Decrements on occurrence of
• Next Channel Sub-revolution Counter Terminal
  Count
• Fine Delay Clock
• Allows configurable number of output pulses per
  trigger event
• No Decrement
• Allows continuous output pulses per trigger event

8
Channel Counters (contd)

• Fine Delay (8 bits)
• Enabled by Sub-revolution Counter Enable
• Clock is delayed by value loaded 500ps and is
• Variable width
• Delay range is 12ns to 139.5ns.

9
Channel Counters (contd)

• Pulse Width Counter (16 bits)
• Enabled by
• Sub-revolution Counter Terminal Count
• Decrements on the occurrence of 32 Frev.
• Pulse Widths from 29.5ns to 1.94ms.

10
Basic Trigger Mode - 1 Pulse Out (Gate)
Channel X
Delay
Pulse Width

• Event Code
• External Input
• VME command

Delay Revolution Count Sub-Revolution Count
Fine Delay
Pulse Width n 32 Frev
Trigger Count 1
11
Basic Trigger Mode - Multiple Pulses Out
Channel X
Delay
Pulse Width

• Event Code
• External Input
• VME command

Delay Revolution Count Subrevolution Count
Fine Delay
Pulse Width n 32 Frev
Trigger Count 4
12
Channel Counters (contd)

• Timestamp (32 bits)
• Reset on occurrence of any Event (configurable)
• Increments on each occurrence of either
• 32 Frev (2 minutes max)
• An Event (configurable)
• Contents are saved on the occurrence of one of
• An Event (configurable)
• First Pulse Output Trigger
• Trigger Counter Terminal Count (last pulse)

13
VMEbus Interface

• Bus Cycles Supported
• A16, D16, D08(OE)
• Address jumper selectable on 2K byte boundary
• Interrupt
• Level and Vector configurable

14
Module Configuration

• Commands
• Module Enable
• Ref Oscillator/Link Clock
• Interrupt Level
• Event Code for Revolution Freq ReSync
• Event Code for Timestamp Reset
• RF Clock Delay

15
VMEbus Interface

• Channel Commands
• Rearm on Halt Trigger
• Trigger (Immediate)
• Reset
• Stop
• Invert Output

16
VMEbus Interface

• Channel Statuses
• Waiting for Revolution Counter Trigger
• Waiting for Revolution Counter TC
• Waiting for Sub-revolution Counter TC
• Waiting for Trigger Counter TC

17
VMEbus Interface

• Channel Interrupts
• Timestamp Trigger Source
• Each channel
• An Event (configurable)
• An Event Link Error
• Carrier (on state change)
• Frame
• Parity
• Trigger Counter TC
• Each channel