Proposal for readout of Forward Detector straw tubes

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Proposal for read-out of Forward Detector straw
tubes

• PANDA DAT requirements
• General layout
• Prototypes

M. Idzik, M. Kajetanowicz, K.Korcyl, G. Korcyl,
H.Kuc, A. Misiak, P.Salabura, J. Smyrski, R.
Trebacz Krakow Panda group
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Straw tubes read-out chain

• Straws 15000 tubes (6 chambers8 planes)
• Max drift time 150 ns, _at_ 500 kHz max averaged
  hit rate pile up lt10, 2-3 ns
  time resolution
• Gain 2 104
• Ar (90)/CO2 (10) mixture

FE

• FE cards (preamp shaper discriminator)
  Sensitivity 3 fC, noise lt1 fC
• based on available ASIC's CARIOCA or new
  development based on LUMICAL (Marek Idzik)
• located on detector frames
• differential output (LVDS)

Common Clock Distribution

• Trigger and Read-our Boards- TRB
• based on HTDC time measurement
  TimeOverThreshold for amplidtude meas.
• time w.r.t external common clock , 780 ps
  binning (low resolution-40 MHz clock)
• Zero suppression Hit detection. Slow control
  interface (i.e EPICS)
• data output via GBit optical link

TRB

• Detector Concentrator Compute Node ATCA
  standard
• several TRB inputs
• Detector memory buffer
• feature extraction cluster and tracklet finding
  i.e based on fired wires numbers and time stamps

Detector Concentrator
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FEE Connection to detector
CARIOCA
? (not decided, yet)
?
NEED LOT OF ATTENTION !!!!
Zdet (f)? (f gt50 MHz) ?L/C370 ? Cdet 9pF/m
(14-18 pF)
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FEE Connection to detector
FEE (LUMICAL) connected to straws (UJ october
2008)
additional resis. ?
FEE cards should be electr. shielded !
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CARIOCA 10

• CARIOCA (IBM 0.25 ?m CMOS6SF ) 8 channels,
  preamp, shaper, BLR, discriminator, differential
  (LVDS) output
• radiation hardness (checked for LHC requirements
  no effects up to 20 Mrad dose)
• Sensitivity at 220 pF for negative pulse 2.3
  mV/fC
• peaking time 14 ns, pulse width 60 ns
• power consumption 25 mW/channel

4 ASIC FEE-UJ2008
CERN -proto
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Characteristic (I) amplitude as a function of
injected charge CARIOCA 10
gain 2,6 mV/fC
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CariocaStraw tube (TOT)
Sr90 source
no source
HV 1500 V
HV 1400 V

• Noise (external pick-up) 8 fC (status last
  year) not satisfactory
• New FEE board (better grounding) em. shielding
  expected to improve situation

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Time Over Threshold energy loss HADES MDC

• Signal height (V) dE/dx

• dE/dx vs momentum

24 7 mm gaps HeIso (21) FEE based on ASD8
chip
Jochen Markert, A.Schmah (GSI)
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Time Over Threshold energy loss resolution
measured by HADES MDC
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Garfield simulations for straws
one straw
average from 20 straws

• ArCO2 (9010) _at_ 2 bars
• HV 1500 V
• charge integration time 100 ns
• perpendicular incidence

Pions 0.8 GeV/c
Protons 0.8 GeV/c
?5-6
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Trigger and Read-out Board

• developed in synergy with HADES experiment
• 128 channel TDC based on HPTDC optional
• On-board DAQ functionality via ETRAX-FS (LINUX
  OS 3 200 MHz processors 100MBit/s Fast Ethernet
  interface)
• Optical Digital link 2GBit/s)
• High speed (15 Gb/s) AddOn-connector (32 LVDS)
• DSP (TigerSharc TS201) for on-line
  triggeralgorithms/pre-processing

AddOn connector
100MBit/s ethernet
LVDS
TTL
TTL
SDRAM
EtraxFS
DSP (TS201)
SDRAM
Virtex4 (LX40)
2GBit/s optical link
HPTDC
HPTDC
HPTDC
HPTDC
Optional
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The TRBv2

• 4 TDC 128 channels (40ps RMS
  resolution)
• FPGA Virtex4LX40
• 4x512Mb SDRAM
• ETRAX FS
• 100Mb/s,TCP/IP
• 2,5 Gb/s optical link
• DSP TigerSharc
• AddOn connector
• DC/DC converters

TDC 2, 3
TDC 0, 1
Optical link
SDRAM
FPGA Virtex4
DSP
DC/DC
ETRAX
SDRAM
Ethernet
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HUB

• Conversion from 2 Gb/s 8/10 bit serial
  transmission to Ethernet protocol (UDP)
• 16 SFPs (Small Form-factor Pluggable
  transceivers) optical connectors
• receive/transmit ie 12 2Gb/s and 4 1Gb
  Ethernet
• FPGA (Lattice SCM 25) with IP core

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TRB
Conversion to Ethernet tested (G. Korcyl)
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Expected rates
pbeam 15 GeV/c, NInt2x107 s-1
.
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HPTDC working mode with free running clock
clock (1MHz)
match. window
T
time

• 1 MHz trigger clock
• 1 ?s matching window (1,2 ?s searching window)
  (T.latencymatch.window)
• Multiplicty of hit/channel ? 0.4 (in window) by
  400 kHz /wire
• hit losses neglegible (concern for gt3
  MHz/channel)
• TDC data leading trailing edge 32
  bits(header TDC id, Event ID, Bunch Id)
• 
  32 bits data TDC id, channel, data 19
  bits
• 
  (pairing mode 12 bits trailing 7
  bits width)
• 
  32 bits(trailer)

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Data flow estimate (example)

• 128 channels/wire plane 4 FEE(32 channels each)
  - 1 TRB card (4x32 channels HPTDC)
• 2.0 Gbit/s link (250 MByte/s )- total max load
  (4 links) 1.0 GByte/s
• average maximal load/TRB (1 HPTDC) 13 MHit/s
  ( 13 hits per trigger/TDC) _at_ 400 kHz rate/wire
• 13 MHits10 Bytes(hittrailing falling edge)
  130 MByte/s

x 8 (wire planes)
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• back-up slides

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Characteristics Amplitude as a function of
injected charge LumiCal (AGH) ASIC
gain 13 mV/fC
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Pulses from detector in LUMIVAL (Rf mode)X- ray
source 55Fe

• HV 1200 V

• HV 1350 V

shape changes because of amplitude saturation
full absorption
after X-ray escape
Pulses from iron source 55Fe, in gas mixture 90
Ar 10 CO2 Visible differences between pulses
from escape peak and main peak, At picture on
the right side pulses saturation of large pulses
is visible
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Cosmic rays straw tube with LumiCal chip and ADC
with gate signal from scintillating detector
noise peak , generated because of larger
scintillator area as compared to straw tube
HV 1300 V, gas mixture 90 Ar 10 CO2
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Detector and DAT requirements

• lack of ONE SPECIFIC hardware trigger signal
• continuously sampling FE (time stamps)
• flexibility in the choice of triggering
  algorithms

• interaction rate 20 MHz
• raw data flow 40 - 80 GB/s
• typ. event size 4 8 kB

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PANDA DAT architecture (one possible choice)

• 2 alternative options
• considered so far
• (K. Korcyl )
• push and pull
• push only

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The HADES DAQ (gt100 TRBs!)
CTS
VME CPU

TRB MDC AddOn
TRB General purpose AddOn
TRB TOF AddOn
TRB Shower AddOn
to the front end electronics
LVL1 Trigger box
TRB RICH AddOn
TRBnet
...
TRB for RPC
TRB HUB AddOn
Parallel Event Building(computers)
Ethernet
TRB for Time Wall,Start,Veto
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HPTDC features

• Used in many HEP experiments. Developed at CERN,
  produced in IBM technology 0.25 ? m CMOS (ibm)
  
• 32 channels multihit TDC with variable
  resolution 785ps, 195ps, 98ps, 25ps (LSB) -
  measurement wrt. free running clock, self
  calibration, double pulse resolution typ. 5 ns
• Max hit rate/channel 2 MHz, Trigger rates up to
  1MHz _at_40MHz clock
• Internal buffer to story hits (max 256 hits/8
  channel)- buffer BUT with 4 deep derandomizer in
  each channel
• individual registration of leading and trailing
  edges inside internal chip buffers- Time over
  Threshold
• Two operation modes
• A TRIGGER MATCHING disabled. The raw time
  measurements from input channels are passed
  unchanged to the read-out fifo and can be readout
  to external buffers. 40 MHz read-out
• B. TRIGGER MATCHING enabled. Hits inside
  pre-programmed window are filtered. Latencies lt50
  ?s
• High rates-gtlow latencies

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HPTDC hit losses
hit rate
25 ns dead time reduces loss by factor 10 at 3
MHz rate