University of Michigan

1

• Key PED Challenges
• David Blaauw
• University of Michigan
• blaauw_at_umich.edu

2
Run Time Leakage

• The Last Leakage Frontier.
• Current approaches
• Sleep mode MTCMOS, ABB, State assignment
• Sub-critical paths Dual Vt, Vdd address
• Variable workload DVS / ABB
• Performance critical gates will become
  increasingly dominant
• Critical paths, buss / interconnect drivers,
  clock nets
• Large gate sizes, low-Vt, high-Vdd assignment
• Low switching activity.
• Need for detailed leakage map of SOC designs

3
Variability

• Exponential dependence of subthreshold leakage on
  Vt
• Super exponential dependence of gate leakage on
  oxide thickness
• Significant increase in variability expected
• Statistical modeling of power and energy
• Few bad regions on chip will dominate
• Likelihood of uniformly good silicon is
  diminishing
• Self tuning / adjusting silicon and circuits

4
Sub-Critical Operation

• Digital mind set has been to guarantee correct
  operation under all circumstances
• Coupling noise, supply integrity, SEU, inter- and
  intra-die variability
• Loss of predictability
• Increasing margins
• Inverse correlation between severity and
  likelihood
• Most sever failures also least common
• Gradual failure behavior
• Statistical analysis of failure behavior
• Architectural / system level correction mechanism
• Power robustness trade-off