ConvergenSC Tutorial

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ConvergenSC Tutorial

• Der-Chun Cherng
• Media IC System Lab, GIEE, NTU

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Goal

• A lab exercise of CoWare ConvergenSC Platform
  Creator
• Include detail steps and settings
• From coding to simulation
• Use an extreme simple example
• No ARM, just a fake controller

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Example System
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Folder Structure
Lab
src SystemC source files
SCW
include SystemC header files
work Working folder of ConvergenSC
Generated by CovergenSC
top Exported System, include system wrapper and
simulation script
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Source Code

• control.cpp
• Controller module
• EdgeDetectionFilter_TLM.cpp
• Edge detection filter module, in TLM
• memory_AHB_TLM.cpp
• Memory model, in TLM
• clockreset.cpp
• Clock and reset generator
• For bus model

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Source Code Explanation

• Stay awake!!

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Step 1. Open Platform Creator

• gt source /setup.csh
• gt cd /SCW/Lab
• gt pct

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Step 2. Build Library

• Library -gt Open
• Open AMBA library for protocol definition
• /usr/cad/CoWare/V2005.1.1/IP/AMBA_BL/ConvergenSC/A
  MBA_BL.xml

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• If successful, the window should look like this

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• Library -gt Import SysyemC Modules

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Add Files and Include path

• Add files
• src/control.cpp
• src/EdgeDetection.cpp
• src/clockreset.cpp
• src/mem_AHB_TLM.cpp
• Add Include Paths
• include
• /usr/cad/CoWare/V2005.1.1/IP/AMBA_BL/SystemC/inclu
  de
• Click OK
• Wait to see if any error occurs
• When error occurs, correct the code and click on
• Library-gtReload SystemC Modules

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• If no error, we should see our modules in system
  library

System library will include the module we import,
and the library components we used from other
libraries
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Modified Module Parameter (1)

• Select a module in System Library
• Choose Block editor at the bottom
• Module Clock
• In column Ports, clk -gt protocol
• Change from Default to CLOCK
• In column Encapsulation, clk-gtmapped to
• Change from --- to clk.pin
• Module Reset
• protocol change from Default to RESET
• mapped to change from --- to rst.pin

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After the protocol is changed, the port needs to
be remap to signals in current protocol.
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Modified Module Parameter (2)

• Select a module in System Library
• Choose Parameter Editor from the bottom
• Module edge_detection_filter
• Find port start_dataout
• Category change from Memory to Control
• Direction Out
• MasterSlaveness Master
• Module Fake_controller
• Find port interrupt
• Category change from Memory to Control
• Direction In
• MasterSlaveness Slave

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Set master/slaveness of an standard sc_in/sc_out
port
Protocols used of an sc_port can be changed in
Block Editor
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Save Library

• File -gt Save System Library as
• Library name edgeLib
• File name edgeLib
• File type xml

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Step 3. Build the System in PCT

• File -gt New
• Library -gt Open
• edgeLib.xml
• /usr/cad/CoWare/V2005.1.1/IP/AMBA_BL/ConvergenSC/A
  MBA_BL.xml
• There will be a opened AMBA_BL in edgeLib too,
  but we can not use the AMBA_BL components from
  edgeLib
• Need to open the original AMBA_BL again

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Drag and Connect Component

• Drag the component from libraries
• AHB
• edge_detection_filter
• Fake_controller
• memory_AHB_TLM
• Clock
• Reset

• Make connections by select connection icon
• i_Clock.clk to i_AHB.clk
• i_Reset.rst to i_AHB.rst
• i_Memory_AHB_TLM.p_AHB to i_AHB
• i_edge_detection_filter.control to i_AHB
• i_edge_detection_filter.data_io to i_AHB
• i_Fake_Controller.control to i_AHB
• i_Fake_Controller.interrupt to i_edge_detection_fi
  lter.start_dataout

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Ports on AHB will be generated automatically
Interrupt is done outside AHB
Port color Black master White slave
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Set Default Master on AHB

• Allowance of multiple masters
• Automatic generated arbiter
• Need to define priority in Parameter Editor
• C_2_s
• default master false
• priority 1
• C_5_s
• default master true
• priority 0

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For master port connection, need to define
priority
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Set Clock and Reset Period

• Select i_Clock and i_Reset in system diagram
• Choose parameter editor from bottom
• For i_Clock
• Modified division to 4
• For i_Reset
• Modified _tick to 37

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Step 4. Create Memory Map

• Right click on the following port and click Add
  to Memory Map
• i_Fake_Controller.control
• i_Memory_AHB_TLM.p_AHB
• i_edge_detection_filter.control
• i_edge_detection_filter.data_io
• Select Memory Map Table from bottom
• Notice that the port we add appear here
• Separate into row and column
• Column Initiator
• Row Target
• The intersection represent the address of a
  traffic from an initiator to a target

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For i_edge_detection_filter.data_io to
i_memory_AHB_TLM.p_AHB set address 0x100000
For i_Fake_Controller.control to
i_edge_detection_filter.control set address 0x0
May select Check -gt Check Memory Map to make
sure assignment is correct
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Export System

• Save
• Export -gt Export System
• Create a new folder top,then export the system
  into it.

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Run simulation

• cd top
• gt scsh
• Enter SystemC Shell
• scshgt source sim.tcl
• Export system will produce a script sim.tcl
  to build the simulation. It takes some time
• scshgt set_maf mem_map
• Import the memory map
• scshgt run

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Analysis of Bus Activity

• scshgt source sim.tcl
• scshgt set_maf mem_map
• scshgt analysis_config_gui on
• scshgt run
• Since analysis is on, simulation stops after
  elaboration
• configuration windows shows
• Check enable analysis

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Enable data collecting
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• scshgt c
• continue simulation
• wait for simulation finished
• scshgt sdviewer transaction_data

Select info to display