Lab2 Adding IP to a Hardware Design Lab: MicroBlaze

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Lab2Adding IP to a Hardware Design Lab
MicroBlaze
2
Objectives

• Add additional IP to a hardware design.
• Implement the design by utilizing ISE.

3
SetUp

• For this lab, you will need a memec design
  V2MB1000 development board and a serial cable.
• Connect the included programming cable to the PC
  parallel port and the V2MB1000 development board
  .
• Connect a serial cable between the PC and the
  DB-9 connector on the board.
• Attach the included power supply to the board.

4
Procedure

• In this lab, you will use the system dialog mode
  of XPS and the text mode features to add the
  following IP to an existing processor system.
• OPB timer and counter for time delay
• OPB GPIO DIP switches

OPB Bus
MDM
UART
MicroBlaze
INTC
LMB BRAM Cntlr
LMB BRAM Cntlr
Timer
BRAM
GPIO
PSB
GPIO
LEDs
7Seg LED
GPIO
GPIO
SWs
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Opening the Project

• Create a lab2 folder in the X\EDKLab\ directory.
  If you wish to continue with your completed
  design from lab1 then copy the contents of the
  lab1 folder into the lab2 folder.

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Opening the Project

• Open XPS, click File ? Open Project and browse to
  the project which is in the directory
  X\EDKLab\lab2, then click system.xmp to open the
  project.

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Add the IP by Using Add/Edit Cores(dialog)

• Click Project ? Add/Edit Cores(dialog)

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Add the IP by Using Add/Edit Cores(dialog)

• Add/Edit Hardware Platform Specifications dialog,
  displaying the processor and peripherals included
  in the system thus far.

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Add the IP by Using Add/Edit Cores(dialog)

• In the right window of the Peripherals tab,
  select each of the following peripherals by using
  the CRTL key
• opb_gpio
• opb_timer

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Add the IP by Using Add/Edit Cores(dialog)

• Click ltltAdd to add the selected peripherals.

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Add the IP by Using Add/Edit Cores(dialog)

• Change the instance names of the opb_gpio and
  opb_timer peripherals (which you just added) to
  DIP_Switches_8Bit and delay respectively, by
  clicking once in the Instance column and typing
  the new name for each desired peripheral.

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Add the IP by Using Add/Edit Cores(dialog)
1.

• Select the Bus Connections tab and set the bus
  connections as listed in the following table.
  Click once in each respective column for the
  corresponding component.

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Add the IP by Using Add/Edit Cores(dialog)

• Select the Addresses tab and change the base- and
  high-addresses of the following listed
  peripherals to the listed values.
• Click the ?? button and the ?? button to accept
  the settings.

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Add the IP by Using Add/Edit Cores(dialog)

• Click Project ? View Block Diagram to view the
  schematic of the design built so far.
• Close the schematic view.

Delay
DIP_Switches_8Bit
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Use Add/Edit Cores(dialog) to Add Additional
Ports and Connect Them
1.

• Click Project ? Add/Edit Cores (dialog) again so
  additional ports can be added.
• Click the Ports tab and type OPB_CLK in the
  Filter substring or instance field. You will see
  instances listed some of the instances will show
  OPB_CLK as they carry the OPB_CLK port.

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Use Add/Edit Cores(dialog) to Add Additional
Ports and Connect Them

• Using the CTRL key, select the OPB_CLK for the
  following instances and click the button.

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Use Add/Edit Cores(dialog) to Add Additional
Ports and Connect Them

• Similarly, add the ports to the peripherals
  listed below. Change the filter substring to
  match the names below, or to display all ports,
  delete the text from the filter string.

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Use Add/Edit Cores(dialog) to Add Additional
Ports and Connect Them

• Scroll down in the left window and make changes
  to the following nets.
• Note These changes are necessary to ensure all
  peripherals are driven by the same clock.

Original Net Name
New Net Name
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Use Add/Edit Cores(dialog) to Add Additional
Ports and Connect Them

• Click the net name field of the Interrupt port of
  the delay instance and make it blank by deleting
  the default net name.
• Note Because this is an output node, it can be
  left floating if it is not used. At this stage,
  you will keep it floating however, in a later
  lab, you will connect it.

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Use Add/Edit Cores(dialog) to Add Additional
Ports and Connect Them

• Right click the GPIO_in port of the
  DIP_Switches_8Bit, then select Make Signal
  External.
• Add Range 07 to DIP_Switches_8Bit_in in the up
  window.

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Use Add/Edit Cores(dialog) to Add Additional
Ports and Connect Them
1.

• Select the Parameters tab, in the Choose IP
  Instance for a list of parameters field, click
  the drop-down box and select delay as the
  instance, which will show the available
  configuration parameters for that instance.

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Use Add/Edit Cores(dialog) to Add Additional
Ports and Connect Them

• Select all of the following parameters related to
  the delay instance and click the Add button to
  add those parameters with the default values.
• Change the C_ONE_TIMER_ONLY value from 0 to 1 as
  you will use only one timer.

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Use Add/Edit Cores(dialog) to Add Additional
Ports and Connect Them

• In the Choose IP Instance for a list of
  parameters field, select DIP_Switches_8bit as the
  instance, which will show the available
  configuration parameters for that instance.
• Select the following parameters and click the Add
  button to add those parameters.

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Use Add/Edit Cores(dialog) to Add Additional
Ports and Connect Them

• Change the default values of the following
  parameters to the new value provided below.
• Click the ?? button to accept the changes.

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Edit the MHS File

• Double-click the MHS File system.mhs entry under
  the Project Files in the System tab.

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Edit the MHS File

• Rename the net connected to the DIP_Switches_8Bit
  instances DIP_Switches_8Bit_GPIO_in name to
  DIP_Switches_8Bit_GPIO_in_pin.

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Edit the MHS File

• Rename the net connected to the delay instances
  OPB_CLK port to sys_clk_s.
• Save the system.mhs file and then close it.

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Edit the MHS File

• We perform this task here simply to demonstrate
  that the text file that represents the system can
  be hand edited if desired. The same result could
  have been achieved within Add/Edit Cores (dialog)
  ports tab.

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Edit the MHS File

• Click Project ? View Block Diagram to view the
  schematic of the design.
• Close the Schematic viewer

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Add Pin Assignments for I/O Signals

• Select the System tab double click on the UCF
  file.

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Add Pin Assignments for I/O Signals

• Add the following lines to the UCF file.
• Net DIP_Switches_8Bit_GPIO_in_pinlt0gt LOCC6
• Net DIP_Switches_8Bit_GPIO_in_pinlt0gt PULLUP
• Net DIP_Switches_8Bit_GPIO_in_pinlt1gt LOCD6
• Net DIP_Switches_8Bit_GPIO_in_pinlt1gt PULLUP
• Net DIP_Switches_8Bit_GPIO_in_pinlt2gt LOCA5
• Net DIP_Switches_8Bit_GPIO_in_pinlt2gt PULLUP
• Net DIP_Switches_8Bit_GPIO_in_pinlt3gt LOCB5
• Net DIP_Switches_8Bit_GPIO_in_pinlt3gt PULLUP
• Net DIP_Switches_8Bit_GPIO_in_pinlt4gt LOCC5
• Net DIP_Switches_8Bit_GPIO_in_pinlt4gt PULLUP
• Net DIP_Switches_8Bit_GPIO_in_pinlt5gt LOCC4
• Net DIP_Switches_8Bit_GPIO_in_pinlt5gt PULLUP
• Net DIP_Switches_8Bit_GPIO_in_pinlt6gt LOCA4
• Net DIP_Switches_8Bit_GPIO_in_pinlt6gt PULLUP
• Net DIP_Switches_8Bit_GPIO_in_pinlt7gt LOCB4
• Net DIP_Switches_8Bit_GPIO_in_pinlt7gt PULLUP

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Add Pin Assignments for I/O Signals

• Save the system.ucf file and then close it.

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Creating a Project Navigator Project

• In XPS, click Options ? Project Options, this
  will open the Project Options dialog.

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Creating a Project Navigator Project

• Select the Hierarchy and Flow tab, Configure the
  dialog to match the options selected shown below,
  which should only involve selecting the ISE
  (ProjNav) radio button. A default ProjNav
  directory has already been chosen.
• Click ?? to close the dialog and apply the
  settings.

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Creating a Project Navigator Project

• Select Tools ? Generate Netlist or click in
  the toolbar.

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Creating a Project Navigator Project

• Once PlatGen has completed, click Tools ? Export
  to ProjNav. This will create the Project
  Navigator project and add the appropriate files.
• Close the project in XPS.

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Implement the Design in the Project Navigator

• Double-click system.npl file in Windows Explorer
  to open the Project Navigator project located in
  the lab2\projnav directory.
• Your project should match follow figure.

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Implement the Design in the Project Navigator

• Toggle the paths in the Sources in Project window
  to make the paths relative rather than absolute.
  This promotes portability of the project into a
  different directory structure. Click on one of
  the sources in the window and select Toggle
  Paths.

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Implement the Design in the Project Navigator

• Add the UCF file to the project. Click Project ?
  Add Source and add the system.ucf from the
  ..\data directory.

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Implement the Design in the Project Navigator

• In ISE, click Edit ? Preferences
• Select the Processes Tab, select Advanced, and
  click OK.

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Implement the Design in the Project Navigator

• In the Sources in Project window, select system.
• In the Processes for Source system window,
  Right-click Implement Design and select
  Properties.

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Implement the Design in the Project Navigator

• Select the Translate Properties tab and verify
  that the macro search path is set to
  ..\implementation.
• Click OK

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Implement the Design in the Project Navigator

• Select system in the Module view and double-click
  Implement Design in the Process view.

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Implement the Design in the Project Navigator

• Once the Implement Design process is completed,
  double-click the View/Edit Routed Design(FPGA
  Editor) under Place Route to view the
  implemented design.

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Implement the Design in the Project Navigator

• Close the FPGA Editor after viewing the
  implemented design.
• In the Processes for Source system window,
  Right-click Generate Programming File and select
  Properties.

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Implement the Design in the Project Navigator

• Select the Startup Options tab and change CCLK to
  JTAG Clock, then click ??.

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Implement the Design in the Project Navigator

• Double-click Generate Programming File to create
  a BIT file.

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Implement the Design in the Project Navigator

• When the Generate Programming File completes, two
  critical files have been generated
• system.bit Located in the lab2mb\projnav
  directory, this BIT file represents the
  implemented processor system.
• system_bd.bmm Located in the lab2mb\implementati
  on directory, this BMM file contains the location
  constraints for the BRAM utilized in the
  processor system. This file is used by Data2BRAM
  to update the BRAM contents with the processor
  application code.
• Close the Project Navigator

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Download the Project to the V2MB1000 Development
Board

• In XPS, click Tools ? Import from ProjNav. This
  will bring the results from Project Navigator
  into the XPS environment. For project
  portability, it is best to use relative path
  names. Make sure the path names point to the
  projnav and implementation directory for BIT file
  system.bit and the BMM file system_bd.bmm
  respectively. Select OK.

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Edit the C File

• Double-click the C File TestApp.c entry under
  the Project Files in the System tab.

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Edit the C File

• Un comment the xil_printf statements in the code,
  then add DIP_Swithes_8Bit code and save it.

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Download the Project to the V2MB1000 Development
Board

• Open a Hyperterminal session with the baud rate
  set to 9600.
• Open ?????????????????????? and select COM1.

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Download the Project to the V2MB1000 Development
Board
1.

• Set ?????, then click ??.

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Download the Project to the V2MB1000 Development
Board

• Click Tools ? Download. This will compile the
  software, merge the HW and SW images, and
  download the merged bit file to the board.

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Download the Project to the V2MB1000 Development
Board

• After the board is programmed, you will see a
  message on the terminal window.

Download is completed!
1 1
0 1
Reset
10101010
11110000
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Conclusion

• XPS can create an MHS file representing the
  processor system. The system can be configured by
  using peripheral parameters and by controlling
  internal and external ports. Once the system has
  been defined, the processor system netlists can
  be created.
• In future labs in this course, you will learn how
  to add user cores, add software to the system,
  simulate the design, debug the software, and
  verify the complete design functionality by using
  a hardware board.