Research and Development for the HFT at STAR

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Research and Development for the HFT at STAR
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STAR HFT

• Two layers
• 1.5 cm radius
• 4.5 cm radius
• 24 ladders
• 2 cm X 20 cm each
• 100 Mega Pixels

Purpose Greatly improve charm hadron capability
in STAR
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RD for the HFT

• The mechanical aspects of this detector require
  significant RD. This is also true for the
  electronics and readout.
• Phased approach gt Development of mechanical
  structures and first generation prototype
  detectors and readout in RD phase.

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Prototype HFT Readout Functional Goals

• Digitize every 20 ns.
• Triggered detector system fitting into existing
  STAR infrastructure.
• Deliver full frame events to STAR DAQ for event
  building at approximately the same rate as the
  TPC.
• Reduce the total data rate of the detector to a
  manageable level (lt TPC rate)
• Reliable, robust, cost effective, etc.

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MimoSTAR Detector Pixel Structure

• Serial raster readout
• 640 pixels in a row
• 320 column / sector
• 2 sectors / detector
• 4 ms readout time (50 MHz pixel read clock)

APS detectors in a wafer
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Prototype HFT Ladder

• 20 I gt V converters / drivers per ladder
• Additional clock, control and JTAG connections.
  Power and ground
• Analog signals and clock/control is transferred
  to the motherboard via fine twisted pair cable.
• All ladders are the same

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HFT Prototype System Functional Block Diagram
The readout system is a large parallel system.
The block diagram shown above is for one ladder
of a 24 ladder system.
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ADC and CDS Block Diagram

• Synchronous Correlated Double Sampling and hot
  pixel removal.
• 8 bit data after CDS.
• SRAM contains a circular buffer that is an
  updating raster scan of 1 frame of sector
  readout.
• Perform read subtract write on each clock
  tick.

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(1 of 20 per ladder)
To Event FIFO
320 pixels deep shift register
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SECTOR EVENT FIFO

• Each Trigger enables an empty Event FIFO for 1
  frame ( 204,800 clocks) with an offset to the
  enable that aligns the event start time with the
  location of the first pixel in the event.
• Each event FIFO is a separate trigger event
  stream and can be enabled independently. This
  allows events to be triggered at 1 ms intervals
  with our 4 ms latency.
• Each sector event FIFO is emptied by the SIU at
  the end of its active frame.

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Implementation Diagram
x5
DAQ
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Data Rates

• 100 hits/cm2 Inner Layer, 20 hits/cm2 Outer Layer
  (L 1027)
• Average event size 90 KB
• Event size 90 MB/sec at 1KHz
• 24 fibers
• 12 RORC (4 readout PCs)

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Ultimate HFT Detector Readout

• Same physical size detector (640 x 640 pixels).
• Ultimate Detectors will have on-chip CDS and
  remotely configurable discriminators (2 bits /
  pixel)
• Integration (frame active) time is 200
  microseconds but the readout time is 1 ms.
• 4 LVDS readout lines / detector

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Ultimate HFT Detector Readout
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HFT Prototype Testing

• Ladders mechanical properties of prototypes and
  STAR environment.
• Readout cable.
• Preliminary air cooling tests.
• Preliminary electronics developments.

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Prototype Ladder
2 candidates
Top layer 50 µm CFC Middle layer 3.2 mm
RVC Bottom layer 50 µm CFC
Outer shell 100 µm CFC Fill RVC
APS (50µm) X0 0.05 (thinning to 50µm is a
standard industrial process) Cable X0 0.09
Carrier X0 0.11 Ladder Total (with
adhesive) X0 0.282
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Prototype Carrier
Plot shows fundamental resonance frequency
measured with a capacitance probe. Measured 139
Hz Calculated 135 Hz
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Thermal Visual Images
Airflow 0 Heaters off
Airflow 0.8 m/s Heaters on
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Si temperature rise 5-7 above ambient No hot
spots, good uniformity in temperature.
Emissivity is OK
Upper test piece is 2 cm x 2 cm x 50 µm thick Si
glued to Pt heater serpentine strip at 100mW/cm2
Lower test piece is 2 cm x 2 cm x 50 µm thick Si
with Resistor heating at 164 mW along the upper
edge and 90 mW distributed over the rest of the
piece More information at http//www.lbnl.leog.org
/ir_prelim_writeup.htm
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Vibration from Air Cooling and the STAR
Environment
Airflow at 10 deg. onto prototype carrier
measured at unsupported end gives measured
location distribution with SD 1.6 µm at 1.0 m/s
of airflow Sensitive accelerometer on FTPC
support shows 10 µm displacements at 1 Hz on
STAR detector.
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Prototype Cable

• 100 traces (2 LVDS pairs / sensor, clk, power,
  gnd, cntl )
• 4 layer design, 25 µm kapton, 20 µm Al conductor
• Impedance controlled signal / clock pairs with
  power and ground geometrically arranged as
  shielding.

Prototype Cu conductor cable
X0 0.090 (for Al conductors)
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Prototype Readout Electronics
FPGA
ADC
SRAM
MIMOSTAR5

• Construction bakelite carrier, cable, 1 x 50 µm
  MIMOSA5 detector, 1 detector (all 4 sectors)
  instrumented with amplifiers and differential
  drivers.
• Motherboard and daughter card. Daughter card has
  ADCs, FPGA, fast SRAM. Provides CDS and memory
  interface. Development platform for cluster
  finding algorithms

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Summary

• Prototype RDO design gives 1 KHz event rate
  despite a 4 ms detector latency by the use of
  multiple parallel buffering of events.
• Design fits seamlessly into the existing STAR DAQ
  and Trigger infrastructure. Data from the HFT
  will be built into unified STAR events.
• Reconfigurable FGPA based cluster finding and
  readout logic.
• Cooling, vibration and radiation length
  challenges appear to be manageable.
• We are starting to implement the required
  functionality into our prototype readout
  electronics.