6' LowPower Static RAM Architectures

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6. Low-Power Static RAM Architectures

• Organization of a static RAM
• Memory Core this structure can access any cell
  by accessing a particular row and a column. A row
  is activated by a global line spanning all cells
  of the row word line. This line enables the
  cells to be written into or read out.

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• Word decoders the set of cells that generate the
  word line signals form the word decoders.
• Column decoders column decoders select
  particular bit lines for being connected to sense
  amplifiers.
• Precharge differential read/write scheme are
  used for memory cells.
• Sense amplifiers these circuits accomplish the
  conversion of bit line differentials to logic
  levels.

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Memory core, word decoders, column decoders,
precharge, sense amplifiers
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Low power SRAM Techniques

• Standby power reduction
• Operating power reduction
• Memory bank partitioning
• SRAM cell design
• Divided word line
• Bit line segmentation
• Reduced bit line swing
• Pulsed word line and bit line isolation

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6.3 MOS Static RAM Memory Cell

• NMOS 4T SRAM cell
• CMOS 6T SRAM cell

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The input-output characteristics of a pairs of
inverters superimposed to show the stable points.
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The resistive load is accomplished by generating
high-valued resistors using undoped polysilicon.
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The supply current drawn by this 6T SRAM cell is
limited to the leakage current of transistors in
the stable state.
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6.4 Banked Organization of SRAMs

• Banking is an organization technique that targets
  total switched capacitance to achieve reduced
  power and improved speed.

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An additional set of decoders is necessary to
select one of B banks.
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Word lines are no longer a single line spanning
all memory cells in a row of the memory core.
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6.5 Reducing Voltage Swings on Bit Lines
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6.5.1 Pulsed Word Lines

• To limit the bit line voltage discharge, it is
  sufficient to enable word lines for precisely the
  time needed to develop the bit cell voltage
  discharge.
• To utilize a pulsed word line to its best
  advantage, we should tailor the width of the
  pulse according to the access time of the RAM.

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This circuit gates the word line and the sense
amplifiers by a pulse generated using delay cells.
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A dummy column in the RAM to time the flow of
signals through the core, which is an additional
column of bit cells, sense amplifier, and support
circuit placed at the side farthest from the word
drivers.
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• The SR flip-flop is set and the word line is
  triggered. Cells along the row are enabled with
  the dummy column being the last cell enabled.
• The high signal from the sense amplifier resets
  the SR flip-flop and turns off the word line.

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6.6 Reducing Power in the Write Driver Circuits

• We would prefer row decoding to be as fast as
  possible, since it directly affects access time
  for a RAM.
• A NAND decoder changes the output of the decoder
  along one row.

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• A NOR decoder activates the outputs of all but
  one row.
• A NOR decoder is consequently faster because of
  the smaller height of the evaluation NMOS stack.
• But, its operation results in N 1 rows changing
  their states

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• If we accept the viewpoint that the NAND form
  decoder is desirable from a power perspective, we
  should attempt to improve the performance of the
  NAND decoder.
• A technique similar to the previously mentioned
  banked architecture for memories may be employed
  for decoder structures.

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The self-timed RAM core can be extended for
obtaining the sense amplifier enable signal.
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• Self-latching sense amplifiers accomplish an
  automatic limiting of currents after sense.
• The structure shown in Fig. 6.16 can be
  visualized as a cross-coupled amplifying inverter
  loop, with additional transistors to transfer bit
  line voltage to the inverter loop.

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A cross-coupled amplifying inverter loop, with
additional transistors to transfer bit line
voltages to the inverter loop.
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High-Speed and Low-Power DesignTechniques for
TCAM Macros

• two techniques are proposed to realize
  high-performance and low-power Ternary CAM for IP
  address lookup.
• One technique is the tree AND-type match-line
  scheme for high search speed.
• The other technique is the segmented search-line
  scheme for low power.

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A search engine realized by a TCAM
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(a) The original cascaded AND-type match-line
circuit (b) Logic transformation
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(a) Parallel (b) 3-level tree, and (c) 2-level
tree AND-type match lines
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Concept of the segmented search-line scheme
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The circuit showing the relationship between the
SC and neighboring TCAM cells
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The proposed TCAM cell
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Simulation model for observing the CSE and (b)
simulation results
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(a) Straightforward and (b) leap-frog
interconnection manners