Consistency Models of Distributed Shared Memory Systems

1
Consistency Models of Distributed Shared Memory
Systems

• Jerzy Brzezinski
• Poznan University of Technology
• Institute of Computing Science

2
Distributed Shared Memory System

• Distributed systems equipped with a software
  component on top of message-passing communication
  environment to provide a shared-memory
  abstraction to the programmers.

3
Data access concepts

• remote access
• relocation
• replication

4
Replication
host
host
processor
processor
network
local cache
processor
host
5
Replication
host
host
processor
processor
network
local cache
processor
host
6
Replication
host
host
processor
processor
network
local cache
processor
host
7
DSM System formal definition

• DSM System ? a set of sequential processes P
  p1, p2, ..., pn , interacting via a set X x1,
  x2, ... , of shared memory locations
• shared memory locations ? read/write objects
• each process has its own replica of the whole set
  X

8
Consistency model

• Consistency models are defined by imposing some
  constraints on the serialisation of the set
  Oi ?OW for each process pi.
• The constraints are given as conditions that the
  serialisations must satisfy.
• The conditions usually restrict the set of all
  possible serialisations.

9
Consistency model properties

• Adequacy
• Restrictiveness

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Classes of consistency models

• General access
• Synchronization access

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General access consistency models

• atomic
• sequential
• causal
• processor
• PRAM
• coherence

12
Sequential consistency definition
13
Sequential consistency example
w2(x)1
?1 w2(x)2
?1 r1(x)1
hv1
r1(x)1
p1
p2
w2(x)1
w2(x)2
w2(x)1
?2 w2(x)2
hv2
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Atomic consistency definition
o 1?RT o 2 ? o1 is finished before o2 starts
15
Atomic consistency example
r1(x)1
r1(x)2
p1
p2
w2(x)1
w2(x)2
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Causal consistency definition
17
Causal consistency example
w1(x)2
?1 w2(x)1
?1 w1(y)1
hv1
?1 r1(x)1
r1(x)1
w1(x)2
w1(y)1
p1
p2
w2(x)1
r2(y)1
r2(x)2
?2 r2(y)1
?2 w1(y)1
?2 r2(x)2
w2(x)1
?2 w1(x)2
hv2
18
PRAM consistency definition
19
PRAM consistency example
w1(x)1
w1(y)1
p1
w2(x)2
p2
r2(y)1
p3
r3(x)2
r3(x)1
20
Coherence definition
21
Coherence example
r1(x)1
w1(x)2
w1(y)1
r1(x)2
p1
p2
r2(x)2
w2(x)1
r2(y)1
r2(x)1
22
Processor consistency definition
23
Processor consistency example
r1(x)1
w1(x)2
w1(y)1
p1
p2
w2(x)1
r2(y)1
r2(x)1
24
Relationships between general access consistency
models
atomic
sequential
causal
PRAM
processor
coherence
25
Synchronization access consistency models

• weak
• release
• scope
• entry

26
Weak consistency

• Access to shared locations
• access operations to global data
• access operations to synchronising variables

27
Weak consistency definition
28
Weak consistency example
r1(x)1
w1(x)2
synch1(s)
r1(x)2
p1
p2
w2(x)1
synch2(s)
r2(x)1
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Release consistency

• Two forms of synchronisation
• mutual exclusion
• acquire
• release
• synchronisation at a barrier
• barrier

30
Release consistency example
w1(x)1
rel1(lock)
acq1(lock)
w1(y)1
p1
p2
r2(x)0
acq1(lock)
r2(x)1
r2(y)0
r2(y)1
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Scope consistency

• Synchronisation connected with scope
• mutual exclusion
• acquire open scope
• release close scope
• synchronisation at a barrier
• barrier close global scope then reopen
• explicit scope operations
• open scope
• close scope

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Scope consistency example
w1(x)1
rel1(lock)
acq1(lock)
w1(y)1
p1
p2
r2(x)0
acq1(lock)
r2(x)1
r2(y)0
r2(y)0
the same scope
33
Entry consistency

• Shared variables are explicitely associated with
  synchronisation objects
• Two kinds of locks are distinguished
• shared lock
• exclusive lock

34
Entry consistency example
r1(x)1
rel1(lock)
acq1(lock, SH)
p1
w2(x)1
p2
acq1(lock, EX)
rel1(lock)
r1(x)1
p3
rel1(lock)
acq1(lock, SH)
35
Conclusions

• DSM systems potentially combine advantages of
  both shared and distributed memory systems
• they make easier the development of parallel
  programs in a distributed environment
• achieving these advantages raises new problems,
  e.g. consistency maintenance