Linear Current Starved Delay Element

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Linear Current Starved Delay Element
ICEST 2005, Ni

• Goran S. Jovanovic and Mile K. Stojcev
• Faculty of Electronic Engineering, Ni, Serbia
  and Montenegro

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Variable delay elements (VDEs)-definition VDEs
are inverterbased circuits used for fine,
precise, and accurate pulse delay control in a
high-speed digital and mixed integrated
circuits.How is achieved variable delay?Using
delay line (DL). A chain of VDEs forms DL.
Definitions of some standard terms

• Where we meet delay lines?
• DLs are constituents of
• DLLs (Delay Locked Loops),
• TDCs (Time-to-Digital Converters),
• VCOs (Voltage Controlled Oscillators),
• PWCLs (Pulse-Width Control Loops), etc.

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Typical Applications of DLs

• DLs are used as constituent in DLLs in order to
• achieve correct synchronization between different
  digital blocks (CPU and SDRAM interface, ...),
• eliminate clock skew and jitter within VLSI ICs.
• Vernier delay patterns implemented as TDCs,
  usually composed with two DLs.
• DLs connected in a ring are building blocks of
  VCO in PLLs.
• DLs are constituents of Duty Cycle Correctors
  (DCCs) in systems with feedback loop.

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Classification of delay line elements

• Variable delay line elements are classified as
• Digital- Controlled Delay Elements (DCDEs)
• realized as series of delay elements of variable
  length (the number of elements in a chain
  determines the amount of the delay).
• Voltage-Controlled Delay Elements (VCDEs)
• efficient in applications where small, accurate,
  and precise amount of delay is necessary to
  achieve.
• VCDEs are realized using
• shunt capacitor,
• current starved.

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Shunt capacitor delay elementcapacitive loaded
inverter
Shunt capacitor delay element (a) scheme
(b) typical characteristic delay in term
of control voltage
Shunt capacitor delay element has the following
disadvantages a) the output capacitor occupies
large silicon area b) the amount of a delay and
the range of voltage regulation are small.
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Current starved delay elementsimplemented using
current inverters
Current starved delay element (a) scheme
(b) typical characteristic delay in term
of control voltage
The current starved delay element has a) simple
structure b) relatively wide delay range of
regulation.
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Common to both VCDLs

• Advantages
• Simple structures
• Fine delay resolution
• Disadvantages
• Shunt Capacitor and Current Starved DLs have
  non-linear transfer function, delay variation in
  term of control voltage
• Problem of VCDL realization was considered by
• Y. Moon, et al., An All-Analog Multiphase
  Delay-Locked Loop Using a Replica Delay Line for
  Wide-Range Operation and Low-Jitter Performance,
  IEEE JSSC, vol.35, No. 3, pp. 377-384, March
  2000.
• M. Maymandi-Nejad, M. Sachdev, A digitally
  Programmable Delay Element Design and Analysis,
  IEEE Trans. on VLSI Systems, vol. 11, No. 5,
  October 2003.
• G. Jovanovic, M. Stojcev, Voltage Controlled
  Delay Line for Digital Signal, Facta
  Universitatis, Series Electronics and Energetic,
  vol. 16. No. 2, pp. 215-232, August 2003...

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What we propose

• Linearization of VCDLs transfer function
• We use Current Starved DE.
• Why
• Simple structure
• Relatively wide range of delay regulation
• How we achieve linear VCDL?
• We modify the bias circuit.
• We use a non-linear bias circuit which is based
  on the square-law characteristics of a MOS
  transistor in saturation.
• By a cascade connection of two non-linear
  elements, the bias circuit and the current
  starved delay element, we obtain a linear
  transfer function (delay in terms of control
  voltage).

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Delay Line Element standard solutionCascade
composition of a bias circuit and VCDL
where tdelay - delay time, C - parasitic output
capacitance, Vsw clock buffer (inverter) swing
voltage, Icp - charging/discharging current of C.
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Bias circuit with reciprocal current
regulation Proposal
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Schematic of a bias circuit
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Analytical model of a bias circuit
Transfer function of current-to-voltage converter
Transfer function of voltage-to-current converter
Reciprocal of Charge-discharge current variation
in terms of control voltage
Charge-discharge current variation in terms of
control voltage
Technological and operating parameters for 1.2 mm
CMOS technology Cox1.41e-3 F/m2 mp195E-4
m2/Vs mn555E-4 m2/Vs kn0.578.255 mA/V2
kp0.527.495 mA/V2 Vtn0.6259V Vtp1.14V
I012.5mA R120kW Vdd5V
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HSpice simulation of a bias circuit
Reciprocal of Charge-discharge current variation
in terms of control voltage
Charge-discharge current variation in terms of
control voltage
LA - is a transistors channel length in
Current-to-Voltage Converter
Relative approximation error of the reciprocal
charge-discharge current variation in terms of
control voltage
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Current starved VCDL with linear delay regulation
- Complete design -
Schematic of four stage DL
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HSpice delay line simulation results relate to
CLKout4
Time delay, tdelay , in term of control voltage
Vdiff
Relative approximation error of time delay,
tdelay , in term of control voltage Vdiff
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Conclusion

• An implementation of a linear VCDL is proposed.
• Current starved DL is used.
• Linearization is achieved by modifying the bias
  circuit of current starved DL.
• HSpice simulation results points to the fact
  that for 1.2 mm CMOS technology high delay
  linearity (error is less then 500 ps) within the
  full range of regulation (from 28 to 55 ns) is
  achieved.
• VCDL is used as a constituent of DLL, TDC, PWCL,
  VCO,

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