The Level 1 SciFi Trigger A Fast Track Trigger implemented with FPGA's

1 / 40
About This Presentation
Title:

The Level 1 SciFi Trigger A Fast Track Trigger implemented with FPGA's

Description:

16 layer SciFi/VLPC tracker (80k channels) 4 barrel / 16 disk Silicon tracker (1M channels) ... Silicon strip detectors, SciFi, trigger processors ... –

Number of Views:111
Avg rating:3.0/5.0
Slides: 41
Provided by: DZE1
Category:

less

Transcript and Presenter's Notes

Title: The Level 1 SciFi Trigger A Fast Track Trigger implemented with FPGA's


1
The Level 1 SciFi TriggerA Fast Track
Trigger implemented with FPGA's
  • Presented by
  • Stefan Grünendahl
  • at the
  • VIth International Conference on Particle Physics
    and Advanced Technology, Como, Oct. 1998
  • Contents
  • The DØ Upgrade
  • Physics Motivation
  • Accelerator Environment
  • The Scintillating Fiber Tracker
  • The SciFi Trigger
  • System Overview
  • The Frontend Board
  • Other Components
  • Status and Conclusions

2
The Fiber Tracker L1 Trigger Group
  • LAFEX/CBPF, Rio de Janeiro, Brazil
  • Mario Vaz - CBPF/LAFEX DEL/UFRJ
  • Northwestern University
  • Paul Rubinov
  • University of California/Davis
  • Sudhindra Mani
  • Fermilab
  • John Anderson,
  • Linda Bagby,
  • Fred Borcherding,
  • Stefan Grünendahl,
  • Dave Huffman,
  • Marvin Johnson,
  • Jameson Olsen,
  • Manuel Martin,
  • Mike Matulik,
  • Pat Sheahan,
  • Kin Yip

3
The Detector
  • calorimeter replacement of preamps/shapers
  • muon system
  • replacement of muon chamber readout electronics
  • Iarocci drift tubes replace forward muon chambers
  • central and forward scintillator pixel layers
    enhance trigger capability.
  • DAQ trigger add track and vertex triggering,
    add buffering, add processing power
  • central tracker
  • 2 T supraconducting coil inside r70 cm
    calorimeter bore
  • lead/scintillator preshower detector with
    fiber/VLPC readout
  • 16 layer SciFi/VLPC tracker (80k channels)
  • 4 barrel / 16 disk Silicon tracker (1M channels)
  • forward tracker/preshower scintillator cells
    with fiber/VLPC readout

The DØ upgrade builds upon the strengths of the
existing detector (excellent calorimetry, muon
coverage) and augments it with a high resolution
Silicon/Scintillating Fiber tracker.
4
Physics Goals
  • Increase samples by factor 20
  • top decays O(1000)
  • Ws O(100,000)
  • Zs O(10,000)
  • Precision Tests of the Standard Model
  • Continuation of present DØ physics
    program, with some shift in emphasis
  • precision measurements
  • (top mass, W mass, ...)
  • Constrain the Higgs Boson Mass
  • improvements to B physics capabilities
  • (Bs mixing, CP violation, )
  • QCD with W, Z, photon
  • Extend the Discovery Reach
  • Significant improvement to physics reach
  • few fb-1 data samples allow significant increases
    in the reach for SUSY, leptoquarks,
    W,Z,anomalous couplings.
  • Extended luminosity (5 - 25 fb-1) intermediate
    mass Higgs

5
Tevatron Impact
  • Impact on DØ
  • Integrated L Þ rad damage in tracking chambers Þ
    replace
  • Shorter bunch crossing interval Þ avoid pileup Þ
    electronics pipeline
  • Systems either Upgraded Cal, Muon,Trig/DAQ
  • or Replaced Tracking System
  • Solutions involve new Detector Technologies
  • Silicon strip detectors, SciFi, trigger
    processors
  • The DØ Upgrade is designed to exploit unique
    opportunities offered by the Tevatron during Run
    II and beyond

6
DØ Tracking
calorimeter cryostat
  • Solenoid
  • 2 Tesla superconducting
  • Fiber Tracker
  • Eight layers Sci-Fi ribbon doublets (x-u or x-v)
  • 77,000 830 mm fibers w/ VLPC readout
  • Silicon Tracker
  • Four layer barrels (double/single sided)
  • Interspersed double sided disks
  • 800,000 channels
  • Preshowers
  • Central
  • Scintillator strips
  • 6,000 channels
  • Forward
  • Scintillator strips
  • 16,000 channels

1.1
1.7
50 cm
1.3 m
7
Fiber Tracker
  • Barrels
  • 8 carbon fiber barrels
  • 20ltrlt50cm
  • full coverage to h 1.7
  • Scintillating Fibers
  • 830 mm Ø, multiclad
  • 2.6 m active length
  • 10m clear waveguide to photodetector
  • radiation hard (100 krad) (10 years _at_
    R 20 cm _at_ 1032 cm-2s-1)
  • Fiber Ribbons
  • 8 axial doublets
  • 8 stereo doublets (2o pitch)
  • Readout
  • 77,000 channels
  • VLPC readout
  • run at low temperature (9 K)
  • fast pickoff for trigger
  • SVXII readout

8
Tracking Trigger
Trigger response for Z ee with 4 min.bias
  • Feed all axial fibers plus preshower into gate
    arrays
  • Trigger if a fiber combination is consistent with
    PT gt (1.5,3,6,8) GeV
  • Tag categories (incl. CPS info) track, isolated
    track, electron, ...

9
Trigger Schematic
10
Trigger Architecture
p-bar
p
Muon
Silicon
SciFi
Calo
L0
PS
L1 Trigger
L1
10 kHz
Trigger Framework
L2 Preprocessors
Global L2 Stage
Buffers
250kb/evt
1kHz
L3 Processors
10-20Hz
tape
11
System Overview
  • L1 System overview
  • Frontend Board (on cassette)
  • VLPC signal discrimination
  • track pattern matching
  • track sorting list building per 4.5 sector
  • Receiver Concentrator system (two crates)
  • list building per octant (L1)
  • list building per sextant (L2)
  • L1-CFTTM and L2pp links
  • L1 CFT Trigger Manager
  • forms trigger (and/or) terms for L1

12
SciFi VLPC Cassette
  • 1024 VLPC channels
  • two FE boards two 4.5 trigger sectors
  • CFT Trigger Boards
  • 480 CFT channels, 32 CPS channels/board
  • 1 SIFT SVX channel per CFT channel housed in 7
    Multi Chip Modules (MCMs)
  • 2 SIFT SVX channels per CPS channel

13
FE Board Signal Flow
  • VLPC
  • (Charge Divider) (for Preshower Detectors)
  • SIFT Discriminator (with SVX) in Multichip
    Module
  • Hit Latch
  • Shipping to/from Neighbour FE Board
  • Tracking FPGA
  • Sorting of Track Lists
  • Shipping to Muon L1 System
  • Preshower Matching
  • Sorting of (matched) Track Preshower Lists
  • Shipping to Receiver Cards

14
FE components SIFT SVX
  • SIFT ASIC by ADEPT IC Design in 0.8 mm
    technology
  • 1 SIFT - SVX channel per CFT Fiber
  • 2 SIFT - SVX channels per preshower channel
  • Housed in 1 MCM (2 trigger thresholds - 1 high
    and 1 low)

timing
15
SIFT Threshold
16
SIFT Gain to SVX
  • SIFT x2 Gain is 0.4 into the SVX
  • x1 Gain is 0.2
  • Very linear

17
Track Finding
  • Use digital output from SIFT, and feed into gate
    arrays
  • Match hit pattern against orbit trajectories for
    all possible tracks from PT of 1.5 GeV/c to
    infinity
  • tracking efficiency baseline algorithm uses 8
    out of 8 layers
  • with an option to require only 7 out of 8 layers
    - at highest Pt
  • Minimize backplane connections Track anchor
    layer is the outer layer (layer 8)
  • A 1.5 GeV/c track can span 2 sectors
  • Hits are transmitted across the backplane from a
    sector on either side (layers 1-7 CPS) for
    track matching

18
Seamless Tracking
  • Seamless tracking requires fiber sharing between
    nearest neighbor sectors
  • 1.5 GeV contained in 2 sectors
  • Layer 1 anchor would require two neighbor sharing
    of CPS

19
Signal Routing
  • Division between 2 FE boards on a cassette
  • Green and Yellow are sent left
  • Red and Yellow are sent right

20
Track Finding (cont.)
Example binning by offset
  • All tracks are binned into 4 Pt bins - boundaries
    are user settable
  • Max of 6 tracks per Pt bin
  • 6 highest Pt tracks are sent to muon
  • Tracks are sent in Pt bin order - highest first
  • Tracks are not Pt ordered within the bin
  • Equations can be adapted to
  • as-built geometry
  • luminosity
  • special triggers

21
Track Binning
  • PT binning yields sharper turn-on than offset
    binning

22
Track Finding (cont.)
  • Problem huge, sparsely populated space of track
    solutions has to be collapsed for output
  • Solution Priority encoding of found tracks only
    the highest (90 eff) and lowest (extra 9 eff)
    Pt tracks per Pt bin are selected for each
    fiber in layer 8 (2 tracks per fiber)
  • Allows fast hardware algorithm
  • Monte Carlo studies indicate only 1 real track
    per fiber is gt98 efficient
  • Need 2 tracks because of extra hits at high
    luminosity which create a fake track (7 points on
    original track and 1 fake)
  • Fake track can be higher or lower in Pt than real
    one

23
FPGAs
  • Example Altera 10K devices
  • 1 LE 4-input gate
  • number of LEs needed 2.5 number of
    equations (track finding) 3 number of
    equations (serialization) I/O
    overhead (input multiplexing)
  • largest devices hold one full PT bin (6
    devices/FE board)
  • alternative 2x2X4 smaller devices)

24
Time to L1 Muon
  • We project that all the tracks are at MUON by
    800ns absolute

25
Trigger Concentrator System
  • Common design for CFT/CPS, FPS and Forward proton
    detector
  • CFTCN, FPSCN, ...
  • Four Board Types in Special Crate
  • Receiver board
  • L1 Concentrator board
  • L2 Concentrator board
  • Controller board
  • L3 Read-Out
  • diagnostics
  • mark and pass ...

26
CFT/CPS Geometry
  • Geometry for the CFT L1 and L2
  • Octants to L1CFT (matches calorimeter geometry)
  • Sextants to L2CFTpp L2STTpp (matches silicon
    geometry)

27
L1 Receiver/Concentrator
  • L1 data is processed for each octant (10 sectors
    45 degrees)
  • Creates 17 sums
  • 16 -- Number of tracks in each of 4 Pt bins,
    cluster(x2), Isolated(x2)
  • Total number of hits in the octant
  • 2 L1 outputs per card so can feed 2 CFTTM trigger
    manager boards (32 AND/OR)
  • Passive splitting would allow up to 4 CFTTM
    trigger manager boards (64 AND/OR terms)

28
L1CFTTM
  • L1 Trigger Manager
  • identical to the one used in muon system
  • sixteen 1 GB/s serial inputs (copper)
  • sixteen AND/OR terms to Trigger Framework
  • can be global terms or e.g. eightfold (per
    octant)
  • FPGA to compute trigger terms from input data
  • Scalable just add more boards...

29
L2CFTCN
  • L2 data is processed by a separate set of boards
  • 60 degree sectors are required for STT
  • does not match 4.5 degree sectors of CFT
  • Create 3 approximately 60 degree sectors in each
    180 degree half -
  • 13 FE sectors (58.5 degrees)
  • 14 FE sectors (63 degrees)
  • 13 FE sectors (58.5 degrees)

30
L2CN
  • L2 Concentrator Board
  • Collects Data from 1 or 2 Receiver Boards
  • Uses token passing to collect data within 2.1 ms
  • Output NOT sorted by Pt within each of the 4 Pt
    bins
  • Therefore very large maximum size of list (48
    tracks)

31
Tracks for L2
  • Sent in Pt bin order
  • but NOT Pt ordered in bin
  • First - Highest bin for all sectors starting with
    first sector
  • Next highest for all sectors
  • Third highest for all sectors
  • Fourth highest for all sectors
  • Transfer stops after track 48

32
To L2STT
  • STT searches SVX data (in L2/L3 event buffer)
    for hits in CFT road
  • Purpose offset vertex trigger
  • Two 60 degree sectors are sent to every L2STT
  • STT selects tracks roads that pass through its
    local silicon -gt this gives a large CFT overlap
    for STT roads
  • It takes less than 5 µs to send the data
  • The maximum number of tracks sent to a given STT
    fiber road card is 48 times 2

33
To L2CFT
  • Each 60 degree sector is sent to L2CFT.
  • Data is identical to that sent to the L2STT

34
Summary
  • Overall design for CFT, CPS and FPS complete
  • New technology (FPGAs) meets
  • Timing constraints
  • allows feeding of L1 info to other detectors
  • Flexibility
  • allows for adaptable thresholds/PT bins
  • allows to load as-built detector geometry
  • Scalability
  • can add trigger terms by adding TM cards

35
backup slides
  • Silicon detector
  • etc.

36
List of Terms
  • CPS - Central PreShower
  • FPS - Forward PreShower
  • CFT - Central Fiber Tracker
  • FE - Front End electronics board
  • SIFT - Scintillating Fiber Trigger chip
  • SVX - SVX2e chip
  • MCM - MultiChip Module
  • L1CFT - CFT Level 1 Trigger
  • TM - Trigger Manager
  • CN - Concentrator System

37
The VLPC
  • Visible Light Photon Counter (VLPC)
  • Avalanche Photo Diode
  • well matched to light from fiber (l 525 nm)
  • quantum efficiency 80
  • fast response, high rate capability
  • SiAs (band gap 0.05 eV)
  • high gain (40,000) , low gain dispersion
  • operates at 8 K lt T lt 10 K, 6 V lt Vbiaslt 7.5 V

38
L1/L2 Trigger Configuration
Cal e / j / Et
CAL
CAL
FPS CPS
PS
PS
Global L2
CFT/ CPS
CFT
Track
SC
Muon
Muon
MDT
PDT
L1 ET towers, tracks consistent with e, m, j
L2 Combines objects into e, m, j
39
Trigger Example
Central Electrons
L2 Terms ET gt 7 GeV Isolation, Shape
Cuts Match Cluster / Track L2 Rate 48 Hz
L1 Terms 1 Central EM tower gt 7 GeV
plus 1 CFT track gt 6 GeV/c
with Matching CPS L1 Rate 220 Hz
L3 Terms ET gt 20 GeV Shape Cuts L3 s
0.01 mb, 2 Hz
40
Front End Crates
  • Directly on cryostat
  • 200 boards (80 CFT Trigger, 76 CFT Stereo, 32
    FPS, 10 CPS Stereo), 4 slots (two cassettes) for
    spares
  • up to 16 boards/crate

Cryostat map
Write a Comment
User Comments (0)
About PowerShow.com