Full Adder

1
Full Adder (1-bit)
A
Sum
B
Cout
Cin
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Anatomy of a Verilog Module
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Anatomy of a Verilog Module
module 
Declare a module
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Anatomy of a Verilog Module
module 
Define a module name
FullAdder 
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Anatomy of a Verilog Module
module 
FullAdder 
(A, B, Cin, Sum, Cout)
Declare the input and output ports
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Anatomy of a Verilog Module
module 
FullAdder 
(A, B, Cin, Sum, Cout)
input A 
Define the input and output ports
input B 
input Cin 
output Sum 
output Cout 
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Anatomy of a Verilog Module
module 
FullAdder 
(A, B, Cin, Sum, Cout)
input A 
input B 
input Cin 
output Sum 
output Cout 
Declare local internal signals
wire AandB, AandCin, xxxx, yyyy, zzzz 
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Anatomy of a Verilog Module
module 
FullAdder 
(A, B, Cin, Sum, Cout)
input A 
input B 
input Cin 
output Sum 
output Cout 
wire AandB, AandCin, xxxx, yyyy, zzzz 
and(AandB, A, B) 
Define circuit using built-in logic
and(AandCin, A, Cin) 
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Anatomy of a Verilog Module
module 
FullAdder 
(A, B, Cin, Sum, Cout)
input A 
input B 
input Cin 
output Sum 
output Cout 
wire AandB, AandCin, xxxx, yyyy, zzzz 
and(AandB, A, B) 
and(AandCin, A, Cin) 
endmodule 
Define the end of the module
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1-Bit ALU
Ctrl(0)
Ctrl
Ctrl(1)
A
Full Adder
Carry Control
Cout
A
Cout
B
B
Sum
Cin
Cin
Other logic
A
Result
41 Mux
A
AandB
B
Anot
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(No Transcript)
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4-Bit ALU
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4-Bit ALU
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4-Bit ALU
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4-Bit ALU
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module ALU1Bit ( A, B, Cin, Ctrl, R,
Cout)
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2-bit vector
module ALU1Bit ( A, B, Cin, Ctrl, R,
Cout)
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module ALU1Bit ( A, B, Cin, Ctrl, R,
Cout)
ALU1Bit ALUBIT0 ( A0, B0, Cin, Ctrl, R0,
Cy0)
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module ALU1Bit ( A, B, Cin, Ctrl, R,
Cout)
ALU1Bit ALUBIT0 ( A0, B0, Cin, Ctrl, R0,
Cy0)
ALU1Bit ALUBIT1 (A1, B1, Cy0, Ctrl, R1,
Cy1)
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module ALU1Bit ( A, B, Cin, Ctrl, R,
Cout)
ALU1Bit ALUBIT0 ( A0, B0, Cin, Ctrl, R0,
Cy0)
ALU1Bit ALUBIT1 (A1, B1, Cy0, Ctrl, R1,
Cy1)
ALU1Bit ALUBIT2 (A2, B2, Cy1, Ctrl, R2,
Cy2)
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module ALU1Bit ( A, B, Cin, Ctrl, R,
Cout)
ALU1Bit ALUBIT0 ( A0, B0, Cin, Ctrl, R0,
Cy0)
ALU1Bit ALUBIT1 (A1, B1, Cy0, Ctrl, R1,
Cy1)
ALU1Bit ALUBIT2 (A2, B2, Cy1, Ctrl, R2,
Cy2)
ALU1Bit ALUBIT3 (A3, B3, Cy2, Ctrl, R3,
Cout)
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module ALU1Bit ( A, B, Cin, Ctrl, R,
Cout)
ALU1Bit ALUBIT0 ( A0, B0, Cin, Ctrl, R0,
Cy0)
ALU1Bit ALUBIT1 (A1, B1, Cy0, Ctrl, R1,
Cy1)
ALU1Bit ALUBIT2 (A2, B2, Cy1, Ctrl, R2,
Cy2)
ALU1Bit ALUBIT3 (A3, B3, Cy2, Ctrl, R3,
Cout)
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module ALU1Bit ( A, B, Cin, Ctrl, R,
Cout)
ALU1Bit ALUBIT0 ( A0, B0, Cin, Ctrl, R0,
Cy0)
ALU1Bit ALUBIT1 (A1, B1, Cy0, Ctrl, R1,
Cy1)
ALU1Bit ALUBIT2 (A2, B2, Cy1, Ctrl, R2,
Cy2)
ALU1Bit ALUBIT3 (A3, B3, Cy2, Ctrl, R3,
Cout)
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module ALU1Bit ( A, B, Cin, Ctrl, R,
Cout)
ALU1Bit ALUBIT0 ( A0, B0, Cin, Ctrl, R0,
Cy0)
ALU1Bit ALUBIT1 (A1, B1, Cy0, Ctrl, R1,
Cy1)
ALU1Bit ALUBIT2 (A2, B2, Cy1, Ctrl, R2,
Cy2)
ALU1Bit ALUBIT3 (A3, B3, Cy2, Ctrl, R3,
Cout)
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module ALU1Bit ( A, B, Cin, Ctrl, R,
Cout)
ALU1Bit ALUBIT0 ( A0, B0, Cin, Ctrl, R0,
Cy0)
ALU1Bit ALUBIT1 (A1, B1, Cy0, Ctrl, R1,
Cy1)
ALU1Bit ALUBIT2 (A2, B2, Cy1, Ctrl, R2,
Cy2)
ALU1Bit ALUBIT3 (A3, B3, Cy2, Ctrl, R3,
Cout)
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module ALU1Bit ( A, B, Cin, Ctrl, R,
Cout)
ALU1Bit ALUBIT0 ( A0, B0, Cin, Ctrl, R0,
Cy0)
ALU1Bit ALUBIT1 (A1, B1, Cy0, Ctrl, R1,
Cy1)
ALU1Bit ALUBIT2 (A2, B2, Cy1, Ctrl, R2,
Cy2)
ALU1Bit ALUBIT3 (A3, B3, Cy2, Ctrl, R3,
Cout)
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module ALU1Bit ( A, B, Cin, Ctrl, R,
Cout)
ALU1Bit ALUBIT0 ( A0, B0, Cin, Ctrl, R0,
Cy0)
ALU1Bit ALUBIT1 (A1, B1, Cy0, Ctrl, R1,
Cy1)
ALU1Bit ALUBIT2 (A2, B2, Cy1, Ctrl, R2,
Cy2)
ALU1Bit ALUBIT3 (A3, B3, Cy2, Ctrl, R3,
Cout)
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module ALU1Bit ( A, B, Cin, Ctrl, R,
Cout)
ALU1Bit ALUBIT0 ( A0, B0, Cin, Ctrl, R0,
Cy0)
ALU1Bit ALUBIT1 (A1, B1, Cy0, Ctrl, R1,
Cy1)
ALU1Bit ALUBIT2 (A2, B2, Cy1, Ctrl, R2,
Cy2)
ALU1Bit ALUBIT3 (A3, B3, Cy2, Ctrl, R3,
Cout)
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module ALU1Bit ( A, B, Cin, Ctrl, R,
Cout)
ALU1Bit ALUBIT0 ( A0, B0, Cin, Ctrl, R0,
Cy0)
ALU1Bit ALUBIT1 (A1, B1, Cy0, Ctrl, R1,
Cy1)
ALU1Bit ALUBIT2 (A2, B2, Cy1, Ctrl, R2,
Cy2)
ALU1Bit ALUBIT3 (A3, B3, Cy2, Ctrl, R3,
Cout)
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module ALU1Bit ( A, B, Cin, Ctrl, R,
Cout)
2-bits
ALU1Bit ALUBIT0 ( A0, B0, Cin, Ctrl, R0,
Cy0)
ALU1Bit ALUBIT1 (A1, B1, Cy0, Ctrl, R1,
Cy1)
ALU1Bit ALUBIT2 (A2, B2, Cy1, Ctrl, R2,
Cy2)
ALU1Bit ALUBIT3 (A3, B3, Cy2, Ctrl, R3,
Cout)
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module ALU1Bit ( A, B, Cin, Ctrl, R,
Cout)
ALU1Bit ALUBIT0 ( A0, B0, Cin, Ctrl, R0,
Cy0)
ALU1Bit ALUBIT1 (A1, B1, Cy0, Ctrl, R1,
Cy1)
ALU1Bit ALUBIT2 (A2, B2, Cy1, Ctrl, R2,
Cy2)
ALU1Bit ALUBIT3 (A3, B3, Cy2, Ctrl, R3,
Cout)
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Vectors in a DO File
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Vectors in a DO File
Force the entire vector at the same time
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Vectors in a DO File
Force the entire vector at the same time
force A 1111 force B 0001
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Vectors in a DO File
Force the entire vector at the same time
force A 1111 force B 0001
Force the vector one bit at a time
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Vectors in a DO File
Force the entire vector at the same time
force A 1111 force B 0001
Force the vector one bit at a time
force Ctrl(0) 0, 1 10ns -r 20ns force
Ctrl(1) 0, 1 20ns -r 40ns
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Vectors in a UCF File
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Vectors in a UCF File
Each bit of a vector must be mapped individually
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Vectors in a UCF File
Each bit of a vector must be mapped individually
NET Ctrllt1gt LOC K13 SW7NET Ctrllt0gt
LOC K14 SW6
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Review of Vector Notation
In a Verilog file Ctrl0 In a DO file
Ctrl(0) In a UCF file Ctrllt0gt