Serial Multiplier

1
Serial Multiplier

• Ann Zhou
• Ying Yan
• Wei Liang
• Advisor David Parent
• May 17th, 2004

2
Agenda

• Abstract
• Introduction
• Why
• Simple Theory
• Back Ground information (Lit Review)
• Summary of Results
• Project (Experimental) Details
• Results
• Cost Analysis
• Conclusions

3
Abstract

• We designed a 5-bit serial multiplier that
  operated at 200 MHz and used 3.8W/cm2 of Power
  and occupied an area of 767x189mm2
• 3.8W/cm2, no cooling is needed

4
Introduction

• Advantages over equivalent parallel multiplier
• Huge reduction in the required hardware
• in applications where high data rates are not
  necessary
• Reduce input and output routing

5
Serial multiplier schematic
6
Project Details

• Hand calculations for the longest path
• Final schematic
• Verilog Waveform and Testbench
• Final layout
• Verification (DRC and LVS)
• Final simulation (post extracted)

7
Longest Path Calculations
Note All widths are in microns and capacitances
in fF
8
One Bit Schematic
9
Schematic
10
Verilog Testbench
11
Verilog waveform
12
Layout
13
Verification
14
Simulations
15
Cost Analysis

• Estimate the time we spent on each phase of the
  project
• verifying logic (four weeks)
• verifying timing (one week)
• layout (two weeks)
• post extracted timing (one week)

16
Lessons Learned

• Verify the logic of the design before layout
• Plan the cell height
• Avoid using metal3 to route power and ground

17
Summary

• We designed a 5-bit serial multiplier that
  operated at 200 MHz and used 3.8W/cm2 of Power
  and occupied an area of 767x189mm2
• Compared with equivalent parallel multiplier, our
  design saved a lot of hardware and area in
  applications not requiring very high data rates.

18
Acknowledgements

• Thanks to Cadence Design Systems for the VLSI lab
• Thanks to Synopsys for Software donation
• Thanks to Professor D.Parent
• Thanks to our EE166 classmates