EECSCS 470

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EECS/CS 470

• Computer Architecture
• Winter 2003

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Goals of the Course

• Advanced coverage of computer architecture
• General purpose processors, embedded
  processors,historically significant processors,
  design tools.
• Instruction set architecture
• Processor microarchitecture
• Systems architecture
• Memory systems
• I/O systems

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Teaching Staff

• Professor Trevor Mudge
• Office Hours
• Monday 130pm class time, after class on
  Wednesday after class Room 2114D EECS
• www.eecs.umich.edu/tnm
• Graduate Research Instructor Vishal Soni
• Office hours
• Tuesdays and Thursdays 115 pm - 315 pm  Room
  2420B EECS

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Grading in 470

• Quizzes (5 each) 10
• Homework 1 5
• Homework 2 10
• Homework 3 25
• Project 30
• Exams (two in class, 10 each) 20

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Time Management

• 3 hours/week lecture
• This is probably the most important time
• 1 hour/week discussion
• 2 hours/week reading
• 2-4 hours/week Homework/ exam prep
• 5 hours/week Project (half semester)
• Total 10-15 hours per week.

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Web Resources

• Course Web Page http//www.eecs.umich.edu/cours
  es/eecs470
• Berkeley CPU Page http//bwrc.eecs.berkeley.edu/
  CIC/
• Class newsgroup
• news//news-server.engin.umich.edu/umich.eecs.c
  lass.470
• Winter term 2003
• EECS GRADUATE STUDENTS
• THE LAST DAY TO DROP A COURSE WITHOUT A "W" IS
  JANUARY 24, 2003
• FROM JAN. 25TH THROUGH MAR. 3RD YOU MAY DROP A
  COURSE AND RECEIVE A "W"
• SIGNATURES REQUIRED FROM INSTRUCTOR ADVISOR
• BEGINNING MARCH 4TH DROPS
• APPROVED ONLY FOR EXCEPTIONAL CIRCUMSTANCES
• ALSO REQUIRES SIGNATURES FROM INSTRUCTOR, ADVISOR
  GRADUATE CHAIR

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Levels of Abstraction

• Problem/Idea (English?)
• Algorithm (pseudo-code)
• High-Level languages (C, Verilog)
• Assembly instructions (OS calls)
• Machine instructions (I/O interfaces)
• Microarchitecture/organization (block diagrams)
• Logic level gates, flip-flops (schematic, HDL)
• Circuit level transistors, sizing (schematic,
  HDL)
• Physical VLSI layout, rectangles, cabling, PC
  boards.

What are the abstractions at each level?
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Levels of Abstraction

• Problem/Idea (English?)
• Algorithm (pseudo-code)
• High-Level languages (C, Verilog)
• Assembly instructions (OS calls)
• Machine instructions (I/O interfaces)
• Microarchitecture/organization (block diagrams)
• Logic level gates, flip-flops (schematic, HDL)
• Circuit level transistors, sizing (schematic,
  HDL)
• Physical VLSI layout, rectangles, cabling, PC
  boards.

At what level do I perform a square root?
Recursion?
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Levels of Abstraction

• Problem/Idea (English?)
• Algorithm (pseudo-code)
• High-Level languages (C, Verilog)
• Assembly instructions (OS calls)
• Machine instructions (I/O interfaces)
• Microarchitecture/organization (block diagrams)
• Logic level gates, flip-flops (schematic, HDL)
• Circuit level transistors, sizing (schematic,
  HDL)
• Physical VLSI layout, rectangles, cabling, PC
  boards.

Who translates from one level to the next?
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Role of Architecture

• Responsible for hardware specification
• Instruction set design
• Also responsible for structuring the overall
  implementation
• Microarchitectural design
• Interacts with everyone
• mainly compiler and logic level designers
• Cannot do a good job without knowledge of both
  sides

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Design Issues Performance

• Get acceptable performance out of system
• Scientific floating point throughput,
  memorydisk intensive, predictable
• Commercial string handling, disk (databases),
  predictable
• Multimedia specific data types (pixels),
  network? Predictable?
• Embedded what do you mean by performance?
• Workstation Maybe all of the above, maybe not

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Calculating Performance

• Execution time is often the best metric
• Throughput (tasks/sec) vs latency (sec/task)
• Benchmarks what are the tasks?
• What I care about!
• Representative programs (SPEC, Byte)
• Kernels representative code fragments
• Toy programs not very useful
• Synthetic programs does nothing but with a
  representative instruction mix.

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Design Issues Cost

• Processor
• Die size, packaging, heat sink? Gold connectors?
• Support fan, connectors, motherboard
  specifications, etc.
• Calculating processor cost
• Cost of device (die package testing) /
  yield
• Die cost wafer cost / good die yield
• Good die yield related to die size and defect
  density
• Support costs direct costs (components, labor),
  indirect
  costs ( sales, service, RD)
• Total costs amortized over number of systems
  sold(PC vs NASA)

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Other design issues

• Some applications care about other design issues.
• NASA deep space mission
• Reliability software and hardware (radiation
  hardening)
• Power also important for my laptop
• AMD
• code compatibility (with Intel)

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Other Issues

• Questions?
• Next time, read all of chapter 1 before lecture
• Sign overrides