Recent Advances in the VTBParagon Modeling Tool

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Recent Advances in theVTB-Paragon Modeling Tool

• H. Alan Mantooth
• September 15, 2004
• Department of Electrical Engineering
• University of Arkansas
• Fayetteville, AR 72701
• http//mixedsignal.eleg.uark.edu

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Outline

• Introduction and Paragon Architecture
• Recent Advances
• Model Reading Technology
• SiC JFET/SIT model Illustration
• Where were heading
• Conclusions

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Introduction

• Importance of Modeling and Simulation
• How to model complex circuits and systems?
• The answer is Hardware Description Languages
  (HDLs) like VHDL-AMS, Verilog-AMS and MAST
• Advantages
• Amount of simulator specific information
  (algorithms, data structures) is avoided in HDL
  programming style
• Flexibility of writing own models for designers
• Mixed-Technology models can be modeled as well
• Able to capture Conservative and Non-conservative
  semantics

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Introduction

• Motivation for Modeling tools
• Power device models are not extensively available
  
• HDL modeling is still programming
• Error prone, tedious, difficult to debug
• Evolving Technology demands new models all the
  time
• Even Simulator vendors find it time consuming to
  add these new models to their existing library
• Concentrate more on design and modeling aspects
  rather than on syntax and semantics
• Designers from different scientific backgrounds
  do not use the same analysis tools or same
  modeling languages
• Behavioral modeling tools like Paragon address
  all the above issues
• Provides language-based, yet language independent
  environment

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Paragon Architecture
Input/Editors
Model Reader
Simulator
XML Database
Technology Managers
Tools/Utilities
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Significance of XML

• XML Extensible Markup Language
• Superset of HTML, simple/flexible/structured
  format
• Lends itself to open source and standardization
• Much XML-based technology already exists
• Example MathML, used for model expressions, is
  becoming de facto standard for math on the web
• Enables sharing models independent of any HDL
• Easier to work with data and is supported by
  major programming languages
• Extensible

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Recent Advances

• VHDL-AMS
• top-down
• bottom-up
• support for MAST Importer
• VTB
• ranges of validity
• initial conditions
• MAST
• bottom-up
• top-down
• Verilog - A

• Model Reader
• MAST
• MODELICA

PARAGON XML
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Model Reading Technology

• MAST Importer

Reader
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Illustration of MAST Importer
-- VHDL-AMS Model of resistor generated by
Paragon -- This is a machine generated code. --
Generated on Thu, 10 Sep 2004 030942 PM library
IEEE use IEEE.math_real.all use
IEEE.electrical_systems.all ------ Model
Interface and Parameters Declaration
------ entity resistor is generic ( rnom real
) port ( terminal p electrical terminal m
electrical ) end entity resistor architecture
Arch1 of resistor is ----------- Branch Variable
Declarations --------- quantity i through p to
m quantity v across p to m begin assert rnom /
0.0 report " rnom must be gt 0" severity
error -------------- Simultaneous Equations
------------- i(v/rnom) end architecture Arch1

• MAST Model
• template resistor p m rnom
• electrical p, m
• number rnom
• branch v v (p, m), i i (p-gtm)
• parameters
• if (rnom 0)
• error("() rnom must be gt 0", instance())
• equations
• i v / rnom

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Illustration of MAST Importer
Simulation Results of a Low Pass Filter model
imported from MAST
Capacitor 1uF Resistor 100 ohm
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Modelica Importer

• Implemented using Component Object Model (COM)
  technology
• Provide a way by which two objects could interact
  with each other by calling each others methods
• Forces the Operating system to see applications
  as objects
• Makes software easier to write and reuse

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Modelica Importer ( COM )
MUTLITRANSLATOR
PARAGON
IDispatch Interface
Open Project
C O M
C O M
Add/Remove File
COM Object
Visible
Build/Run
Client
Server
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Modelica Importer (Capacitor model)

• model Capacitor "Ideal linear electrical
  capacitor"
• extends Modelica. Electrical. Analog. Interfaces.
  OnePort
• parameter Capacitance C1 "Capacitance"
• equation
• i C der (v)
• end Capacitor

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SiC JFET/SIT Model

• 3 terminal device
• Operation in Unipolar mode Majority carrier
  device - electrons
• Presence of PN junction causes depletion in
  interface that grows or
• shrinks according to the bias applied

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SiC JFET/SIT Model ( parameters )
Model Interface Editor
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SiC JFET/SIT Model ( Topology )
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SiC JFET/SIT Model
Channel Current
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SiC JFET/SIT Model (25 C)
Measured data
Simulation
Vgs 0v
-1v
-2v
-3v
-4v
Measured data and Simulation results for 25 C
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SiC JFET/SIT Model (100 C)
Vgs 0v
Measured data
Vgs 0v
Simulation
-1v
-1v
-2v
-2v
-3v
-3v
-4v
-4v
Measured data and Simulation results for 100 C
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BSIMSOI Model Topology

• Large Signal topology of
• BSIMSOI, v 2.2 MOSFET model
• 5 external connection points
• 1 internal body node

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BSIMSOI Model ( in Paragon )
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BSIMSOI Model ( Simulation Results)
Ids-Vds characteristics of BSIMSOI Verilog-A
model simulated in Spectre
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Where were heading ( Model Compilation )
MCAST University of Washington ADMS Motorola
Paragon User Interfaces HDLs
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Where were heading

• Developing and validating more Power
  Semiconductor device models into VTB and Paragon
• Automatically create Symbol file (.vi3) for VTB
  models
• Support for Complicated Modelica Mixed-Technology
  models
• Integrating Spice C code generator
• Place the modeling methodology, XML schema in
  public domain
• Reading of models from VHDL-AMS and Verilog-AMS
• Model characterization tools
• Event-driven model development tools

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Where were heading
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Conclusions

• Paragon enables the designer or model supplier to
  more quickly create new models and reuse parts of
  existing models
• BSIMSOI model was implemented in 2 weeks and EKV
  2.6
• MOSFET model in 6 days
• New compact semiconductor device models will be
  available for SPICE and SPICE-like simulators
• The generated C code can be at least as fast or
  faster than hand written codes
• More and more models can be imported with
  Paragons model reading technology