Proc. of the Design, Automation and Test in Europe,

1
The design of an asynchronous VHDL synthesizer
Sun-Yen Tan, Stephen B. Furber andWen-Fang
YenDepartment of Computer Science,University
of Manchester, UK Department of Electronic
EngineeringNational Taipei University of
Technology, Taiwan

• Proc. of the Design, Automation and Test in
  Europe,
• 1998, pp. 44-51.

2
Motivation

• The delay problem in micropipelines
• datapath delays must be less than delays in
  transmitting the request signal.
• special delays are required for significant
  processing logic
• Design tool needed
• most designs are done by hand
• VHDL is an IEEE standard HDL

3
Outline

• Background
• Asynchronous design, micropipelines, previous
  work, VHDL
• The synthesizer
• Structure, partition rules, conversion rules,
  rules for producing control circuits
• Experimental Results
• Conclusion

4
Asynchronous design

• Asynchronous circuits are attracting renewed
  interest
• Avoid the clock problem.
• work at Average case not Worst case.
• A modular approach, micropipelines.
• reduces design time and cost.
• No need to change the interconnections
• whenever better designs are replaced.
• developing high performance and low power
  microprocessing systems.

5
Micropipelines

• (I E Sutherlands Turing Award Lecture,
• Communications of the ACM, June 1989)

Request
Sender
Receiver
Data
Acknowledge
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Two-phase bundled data convention
(1)
Data
valid data
valid data
(2)
Request
req
req-
(2)
req
(2)
(3)
Acknowledge
ack-
ack
(3)

• The operating cycle is (1) data available (2)
  request event, and (3) acknowledge event

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Event-driven logic modules
8
A micropipeline stage
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Previous work

• Burns 1988 CSP to self-timed circuits
• Brunvand 1989 OCCAM to Delay-Insensitive
  Circuits
• Philips 1993 Tangram to handshake circuits
• Nedelchev 1995 OCCAM(async) to asynchronous
  circuits

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VHDL

• VHDL as the input and output models
• VHDL is IEEE standard 1076-1987.
• Event-driven logic modules have been modelled
  individually using VHDL.
• Input or output models written using VHDL are
  easily simulated and their functions verified.

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Structure of the synthesizer
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Synthesis steps

• Partition the statements.
• Analyse the statements within each stage to
  obtain synthesis information.
• Convert all statements into internal circuit
  models.
• Produce the relevant control circuits for each
  stage.
• Produce the interconnections between stages.
• Produce the structural VHDL and Verilog models.

13
Implementation

• Using C.
• Classes and their member functions are defined to
  handle the input descriptions, such as String and
  StringList.
• To represent the internal circuit models, classes
  and their members are also defined, such as
  Terminal, Device, DeviceList, TerminalList,
  Stage, StageList.

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Partition rules (1)

• If the output variables or the output signals
  from a set of non-LOOP statements are not input
  variables or input signals to the other
  statements, these statements can be evaluated
  concurrently.
• This means they can be put into the same stage.

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Example

• An input VHDL program

one stage
another stage
Connect to external signals
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Partition rules (2)

• If a statement contains shift operations
• it will be put into a stage on its own.
• If a statement is a LOOP statement,
• such as FOR or WHILE,
• it will be put into s stage on its own.
• If an IF statement contains
• unbalanced assignments on its THEN and ELSE
  branches
• it will be put into its own stage.

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Conversion rules

• Expression at RHS of expression
• a value, a mathematical, or a logical expression
• in each case, create appropriate objects of
  Device class
• IF statements with balanced THEN and ELSE
  branches
• objects of Devices class denote multiplexers and
  connections.
• For multi-level IF statements
• FILO method is used to calculate the position of
  the multiplexer.
• One signal or variable may appear at LHS of
  several different assignments
• a selector is applied
• if assignments with the same LHS is more than one.

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Rules for producing control circuits (1)

• A stage without SHIFT operation, LOOP statement
  or unbalanced IF statements its control
  circuits are the same as the simple stage.

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Rules for producing control circuits (2)-- The
control circuit for a WHILE loop
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Rules for producing control circuits (3)-- The
control circuit for a SHIFT loop
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Rules for producing control circuits (4)

• Following the configuration of a stage, it is
  necessary to connect its control signals to its
  predecessor and successor stages.
• Some event-driven logic modules are required for
  these interconnections between stages.

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Experimental results

• Part of small floating processor with a 4-bit
  exponent and 5-bit mantissa was used to test the
  synthesizer.
• The circuit was automatically partitioned into 3
  stages by the synthesizer.
• 3 structural VHDL and their entity files were
  automatically generated for the 3 stages.
• A structural VHDL file for the whole system was
  produced.
• All the output files execute on the Leapfrog VHDL
  simulator without error.
• The expected output values and waveforms are
  produced.

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Experimental results
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The numbers of components and internal signals
inside each synthesized VHDL file
25
Conclusion

• A synthesizer has been developed
• converts behavioural VHDL into asynchronous
  structural VHDL and Verilog
• following the micropipeline design style.
• At the high level the computations of a whole
  system can be treated as
• one computation block with micropipelined
  latches.
• helps the designer estimate the behaviour of
  system early using a VHDL simulator.