Outline

1
Outline

• Detector data
• Technologies
• Front-End Electronics
• 180nm chip
• 130nm chips
• Future plans

2
Silicon strips parameters

• 4-5 106 Silicon strips
• 10 - 60 cm long
• Thickness Inner 150-200mm
• Outer -400mm
• Strip pitch 50 mm
• Inner Double sided Cz AC coupled
• Outer Single sided FZ DC coupled

3
Silicon strips data at the ILC

• Pulse height Cluster centroid to get a few
  µm position resolution
• Detector pulse analog sampling
• Time Two scales
• Coarse 150-300 ns for BC identification,
  80ns sampling
• Shaping time of the order of the
  microsecond
• Fine nanosecond timing for the
  coordinate along the strip
• 10ns sampling
• Not to replace another layer or double
  sided
• Position estimation to a few cm using
  pulse reconstruction from samples
• Shaping time 20-50 ns

4
Coordinate along the strip
SPICE
L 28nH R 5 W
Ci500 fF
15 ns
90cm
V 6 107 m/s c/5
Cs 100 fF
1 ns time resolution is 6 cm

5
Measured Pulse Velocity
Measured velocity 5.5cm/ns Measured moving a
laser diode along 24 cm
6
Outline

• Detector data
• Technologies
• Front-End Electronics
• 180nm chip
• 130nm chips
• Future plans

J-F Genat, LECC06, Valencia, Sept 25-29th
2006
7
Technologies

• Silicon detector and VLSI technologies allow to
  improve detector and front-end electronics
  integration
• Front-end chips
• Thinner CMOS processes 250, 180, 130, 90 nm
  now available
• SiGe, less 1/f noise, faster
• Chip thinning down to 50 mm
• More channels on a chip, more functionalities,
  less power
• Connectivity
• On detector bump-bonding (flip-chip)
• 3D
• Smaller pitch detectors, better position and time
  resolution.
• Less material

8
Outline

• Detector data
• Technologies
• Front-End Electronics
• 180nm chip
• 130nm chips
• Future plans

J-F Genat, LECC06, Valencia, Sept 25-29th
2006
9
Integrated functionalities

• Full readout chain integration in a single chip
• - Preamp-shaper
• - Trigger decision (analog sums)
  compact data
• - Sampling Analog pipe-lines
• - On-chip digitization
• - Buffering
• - Digital Processing Centroids and Least
  Squares time/amplitude estimation
• - Calibration and calibration management
• - Power switching
• Presently 128 channels (APV, SVX) chips, 256-1024
  envisaged

10
Front-End Chip

• Integrate 512-1024 channels in 90nm CMOS
• Charge Amplifiers 20-30 mV/MIP over 30 MIP
• Shapers - slow 500 ns 1 ms
• - fast 20-50 ns
• Zero-suppression threshold the sum of
  adjacent channels
• 2D analog memory - 8-16 samples
• 80 ns and 10 ns sampling clocks
• - Event buffer 16-deep
• ADC 10 bits
• Buffering
• Calibration
• Power switching saves a factor 100-200

• ILC timing 1 ms 3-6000 trains
  _at_150-300ns / BC
• 200ms in between

11
Foreseen Front-end architecture
trigger
Channel n1
Sparsifier
S aiVi gt th
Wilkinson ADC
Calibration Control
Time tag
reset
Channel n-1
reset
Analog samplers, slow, fast
Strip
Ch
Storage
Waveforms
Counter
Preamp Shapers
Charge 1-40 MIP, Time resolution BC tagging
150-300ns, fine 1ns
Technologies Deep Sub-Micron CMOS 180-130nm
Future SiGe /or deeper DSM
12
Outline

• Detector data
• Technologies
• Front-End Electronics
• 180nm chip
• 130nm chips
• Future plans

J-F Genat, LECC06, Valencia, Sept 25-29th
2006
13
Silicon
- Preamp - Shaper - Sample Hold - Comparator
3mm
16 1 channel UMC 180nm chip (layout and
picture)
14
Process spreads
Process spreads 3.3 (same wafer)
Preamp gains statistics (same wafer)
15
Shaper output noise
375 e- RMS
375 e- 10.4 e-/pF input noise with chip-on-board
wiring 275 8.9/pFsimulated
16
Tests Conclusions
12 chips tested (end 2005) The UMC CMOS
180nm process is mature and reliable -
Models mainly OK - Only
one transistor failure over 12 chips -
Process spreads of a few 90Sr Source tests
vs VA1 chip from Ideas results OK. Very
encouraging results regarding CMOS DSM
go to 130nm
17
Outline

• Detector data
• Technologies
• Front-End Electronics
• 180nm chip
• 130nm chips
• Future plans

18
Front-end in CMOS 130nm

• 130nm CMOS motivations
• Smaller
• Faster
• - More radiation tolerant
• - Less power
• - Presently dominant in the IC industry
• Features
• - Design more constraining (Design rules)
• - Reduced voltage swing (Electric field
  constant)
• - Leaks (gate/subthreshold channel)
• - Models more complex, sometimes still not
  accurate

19
UMC Technology parameters

• 180 nm 130nm
• 3.3V transistors yes
  yes
• Logic supply 1.8V
  1.2V
• Metals layers 6 Al
  8 Cu
• MIM capacitors 1fF/mm² 1.5
  fF/mm2
• Transistors Three Vt options Low
  leakage option

20
130nm 4-channel test chip
Channel n1
Zero-suppression
Can be used for a trigger
S aiVi gt th
Time tag
Ramp ADC
Channel n-1
reset
reset
Analog samplers, (slow)
Strip
Ch
Preamp Shaper DC servo implemented for DC
coupled detectors
Waveforms
Counter
UMC CMOS 130nm
Received in 2006 Being tested Analog OK,
Digital under tests
Clock 3-96 MHz
21
Analog pipeline simulation
22
Silicon
180nm 130nm
Picture
23
Possible issues noise 130nm vs 180nm
(simulation)

• PMOS

180nm gm944.4uS1MHz ? 3.508nV/sqrt(Hz) Thermal
noise hand calculation 3.42nV/sqrt(Hz)
130nm gm815.245uS1MHz ? 7.16nV/sqrt(Hz) Therma
l noise hand calculation 3.68nV/sqrt(Hz)
Measurements show 2 times better results
24
130nm-1 tests results
Gain OK 30 mV/MIP OK Dynamics 30
MIPs _at_ 5 OK Peaking time 0.8 2ms
0.7 - 3 ms
Power (Preamp Shaper) 300 mW
Noise comparative 130nm _at_ 0.8 ms 850
14e-/pF 130nm _at_ 2 ms
625 9e-/pF 180nm _at_ 3 ms 360 10.5
e-/pF
25
130nm-1 conclusions

• Good matching wrt simulation
• Except noise which is
• much better !
• - Still lot of work to test pipe-line and
  digital
• Statistics from two wafers (70 chips)
• Very encouraging results

Go to 90 nm ?
26
Some issues with 130nm design

• Noise models pessimistic, Silicon actually
  much better !
• Design rules more constraining
• Some design rules (via densities) not
  available under Cadence
• Calibre (Mentor) required

27
130nm-2

• One channel version with
• ServoDC
• Improved pipe-line
• DAC

Layout Picture One channel 1.5
x 1.5 mm2
28
130nm-2 architecture
DC servo to accommodate DC coupled detectors,
DAC, Improved pipe-line
Preamp Shaper
Analog sampler
DC reference
Received January 5th 2007 Test card under
wiring Test stand under work
29
Outline

• Detector data
• Technologies
• Front-End Electronics
• 180nm chip
• 130nm chips
• Future plans

30
Next developments

• Implement the fast (20-50ns shaping) version in
  Silicon-Germanium
• including
• - Preamp Shaper (20-100ns)
• Fast sampling
• Submit a full 128 channel version in 130nm CMOS
  including
• slow and fast analog processing, power cycling,
  digital

31
Planned on-chip digital

• Chip control
• Buffer memory
• Processing for
• - Calibrations
• - Amplitude and time least squares estimation,
  centroids
• Tools
• - Digital libraries in 130nm CMOS available
  (VST)
• - Place Route tools Cadence design kits
  
• from Europractice (Leuven, Belgium)
• - Synthesis from VHDL/Verilog
• - Some IPs PLLs, SRAM

32
The End
J-F Genat, LECC06, Valencia, Sept 25-29th
2006
33
backup
J-F Genat, LECC06, Valencia, Sept 25-29th
2006
34
Beam-tests at DESY
October 2006
J-F Genat, LECC06, Valencia, Sept 25-29th
2006
35
Wiring Detector to FE Chips
Wire bonding Flip Chip
Technology
Courtesy Marty Breidenbach (Cal SiD)
OR (later)
J-F Genat, LECC06, Valencia, Sept 25-29th
2006
36
Wiring Detector to FE Chips
Courtesy Ray Yarema, FEE 2006, Perugia
J-F Genat, LECC06, Valencia, Sept 25-29th
2006
37
3D Wiring
Courtesy Ray Yarema, FEE 2006, Perugia
J-F Genat, LECC06, Valencia, Sept 25-29th
2006
38
Linearities (180nm)
/-1.5 /-0.5 expected
/-6 /-1.5 expected
J-F Genat, LECC06, Valencia, Sept 25-29th
2006
39
Manuel Lozano (CNM Barcelona)Chip connection

• Wire bonding
• Only periphery of chip available for IO
• connections
• Mechanical bonding of one pin at a time
• (sequential)
• Cooling from back of chip
• High inductance (1nH)
• Mechanical breakage risk (i.e. CMS, CDF)
• Flip-chip
• Whole chip area available for IO connections
• Automatic alignment
• One step process (parallel)
• Cooling via balls (front) and back if required
• Thermal matching between chip and substrate
• required
• Low inductance (0.1nH)

J-F Genat, LECC06, Valencia, Sept 25-29th
2006
40
Manuel Lozano (CNM Barcelona)Bump bonding
flip chip technology

• Electrical connection of chip to
• substrate or chip to chip face to face
• flip chip
• Use of small metal bumps
• bump bonding

CNM

• Process steps
• Pad metal conditioning
• Under Bump Metallisation (UBM)
• Bump growing in one or two of the
• elements
• Flip chip and alignment
• Reflow
• Optionally underfilling

J-F Genat, LECC06, Valencia, Sept 25-29th
2006
41
Manuel Lozano (CNM Barcelona)Bump bonding
flip chip technology

• Bumping technologies
• Evaporation through metallic
• mask
• Evaporation with thick
• photoresist
• Screen printing
• Stud bumping (SBB)
• Electroplating
• Electroless plating
• Conductive Polymer Bumps
• Indium evaporation

• Expensive technology
• Especially for small quantities
• (as in HEP)
• Big overhead of NRE costs
• Minimal pitch reported 18 µm but ...
• Few commercial companies for fine
• pitch applications (lt 75 µm)

J-F Genat, LECC06, Valencia, Sept 25-29th
2006
42
Noise 130nm vs 180nm(simulation)

• NMOS

130nm W/L 50u/0.5uIds48.0505u,Vgs260mV,Vds1.
2Vgm772.031uS,gms245.341uS,gds6.3575uS1MHz
--gt 24.65nV/sqrt(Hz)100MHz --gt
5nV/sqrt(Hz)Thermal noise hand calculation
3.78nV/sqrt(Hz)
180nm W/L50u/0.5uIds47uA,Vgs300mV,Vds1.2Vgm
842.8uS,gms141.2uS,gds16.05uS1MHz --gt
4nV/sqrt(Hz)10MHz --gt 3.49nV/sqrt(Hz)Thermal
noise hand calculation 3.62nV/sqrt(Hz)
J-F Genat, LECC06, Valencia, Sept 25-29th
2006