TELL1 for Outer Tracker

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TELL1 for Outer Tracker
Dirk Wiedner, Physikalisches Institut der
Universität Heidelberg Guido Haefeli , EPFL
(Lausanne)
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Data flow TELL1
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(No Transcript)
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Outer Tracker Tasks

• Development of the O-RxCards
• Outer Tracker specific FPGA software
• Synchronization
• OT hits/clusters

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HLT dataflow
64 KEvent DDR SDRAM
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Synchronization (1/2)

X12
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Synchronization (2/2)

• Clock phase Synchronization
• TLK deserializer phase locks on data RxClk
• Preprocessing FPGA uses RxClk for Data input
• Word Synchronization
• Data Valid issued by OTIS at power up or reset
  IEEE 803.2 IDLE
• Event Synchronization
• OTIS Comma before every event (sequence)
• OTIS Header OTIS-ID, BxCounter, Event Counter

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TELL1 Emulation

• TELL1 FPGA on Stratix-PCI board
• OT Software developed in Dresden and Heidelberg
• Compatible to TELL1 VHDL project

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Software Status

• Template for sub detector software created at
  Lausanne
• Data acquisition with Stratix-PCI board starts to
  work (Heidelberg/Dresden)
• Full integration of Outer Tracker Software in
  TELL1 VHDL software project this summer

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Hardware Status

• 4 optical link readout on Stratix-PCI board under
  preparation Local Readout
• 2 TELL1 boards partially tested and running well
  (Lausanne)
• Preproduction of 15 TELL1 boards this summer
• TELL1 boards from preproduction foreseen to be
  tested by participating sub detectors