BEE

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BEE INSECTA Afterlife of SSHAFT

• Chen Chang, Kimmo Kuusilinna, Brian Richards

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Is SSHAFT Dead?
lives As ...
No,
BEE INSECTA
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The Complete Design Environment
Analog Front-end
Network
LVDS/LVTTL
Dedicated Ethernet
BEE/Insecta Design Flow
FPGA Bit Stream Conf File
Simulink MDL
ASIC Layout
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Design Flow 101 Users Perspective
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Virtual Component Library

• Parameterized system level blocks
• Bit-width
• Pipeline stages (latency)
• Output bits truncation

• Customizable block set library
• Different Architecture
• Different Technology Target

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Basic Blocks
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Communication DSP Blocks
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Control Logic Design
VHDL
SF2VHD

• Simulink level StateFlow diagram, encapsulated
  in a subsystem with Xilinx gateways
• Two version of SF2VHD
• V1 C program
• V2 Matlab program

Black Box
StateFlow
Control Signals
Controller
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Testing and Debugging

• Design has to include the test vector generator
  or ROM
• Xilinx ChipScope core is used to observe the
  outputs
• Limited by the available on-chip block RAM

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How to get started?

• Documentation web site
• http//bwrc.eecs.berkeley.edu/Research/BEE
• Tutorials
• Lesson 1 Flow Basics
• Lesson 2 Runtime Debug on BEE
• Outlook design flow forum
• On BWRC exchange server
• Access from the public folder in MS Outlook
• Advanced Chip Design Group mailing list
• chippers_at_bwrc.eecs.berkeley.edu

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Current Status

• Xilinx System Generator V2.2 is the current
  default library
• Migration path available for V2.1 to V2.2
• BEE_ISE V1.01 INSECTA V2 releases stabilized
• ST 0.13um technology is the default ASIC target
• 4 BEE units are in service
• 6 Win2K servers are available for design flow
  usage
• 5 BWRC research groups, 16 students are using
  the current BEE/Insecta flow

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Sneak Peek of the Future

• New and improved user testing and debugging
  environment
• Control all BEE functions from Matlab
• Runtime upload / download data
• Utilizing off-chip SRAM
• Precision step clock control

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BEE Compiler Framework

• Increase Design Scalability
• High-level blocks
• Vector Signals
• Reduce design time
• Faster run time
• Efficient/partial synthesis
• Modular design reuse
• Feature additions
• Tri-state pads/signal support
• Global pad assignment
• Automatic design partition
• Script based hardware generator

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ASIC Flow INSECTA

• Replaces ICMake
• Tcl/Tk code drives the flow
• Same scripting language used by several EDA
  tools First Encounter, Nanoroute, ModelSim,
  Synopsys
• GUI controls technology selection, parameter
  selection, flow sequencing
• A real Push Button flow
• Users can refine flow-generated scripts

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ASIC Tool Flow Placement

• Internally developed ASIC flow
• First Encounter (FE)
• Nanoroute
• Physical Compiler
• Timing Driven!
• FE provides accurate wire parasitic estimates
• Placement by FE or Physical Compiler

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ASIC Flow Routing in 130nm

• Nanoroute Ready for 130nm, 90nm designs
• Stepped metal pitches
• Minimum area rules
• Complex VIA rules
• Avoids antenna rule violations
• Cross-talk avoidance to be evaluated
• Silicon Ensemble Fallback position
• Apollo tools Supported by STM, available soon

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ASIC Flow Back-end

• Using Unicad backend directly for DRC, LVS,
  Antenna rule checking
• Easier to track technology updates from ST.
• Critical for evaluating internally developed
  technology files for FE, Nanoroute

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ASIC Flow Development Activities

• LEF/DEF files for NR, FE
• LEF inadequate for 130nm
• FE Tech, I/O files
• Export from FE/NR to DFII
• Loss of labels, pins
• DRC/LVS
• Modify Calibre decks to address data loss

• Coming Soon! (with your volunteer assistance
  welcome)
• Nanosim, Pathmill
• Cadence SOC22 (FE with NR, wroute, ICC routers
  included
• OpenAccess DB (Genesis) coming soon
• Avanti/Physical Compiler

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Conclusion
If you plan to make a chip, we are here to help
you!
(Volunteers welcome!)
Intensive labor involved, use at your own risk.