What this class is about

1
What this class is about

• Standard Cell ASIC Design Flow
• The process is the class
• We will learn it by doing it
• Languages
• VHDL and some Verilog
• TCL (Tool Command Language)
• Perl (Practical Extraction and Reporting
  Language)
• Bash shell script

2
What this class is about

• Main Topics
• Top Down/Bottom Up Design Philosophy
• Designing with HDLs
• Logic Synthesis with HDLs
• Writing synthesis constraint files
• Creating a testbench
• Automation of the chip build process
• Design for test (DFT) with full scan test
  insertion

3
What this class is about

• Why study how to build a ASIC?
• Fundamental to understanding custom digital chip
  design
• Why not FPGA, Gate Array, Structured Array
• Std Cell design exposes all the critical aspects
  of custom digital design

4
What this class is about

• Environment
• COE Linux machines
• Major Tools
• Modelsim (vcom, vlog, vsim)
• HDL compilation, HDL and gate level simulation
• Design Compiler (dc_shell-xg-t)
• HDL synthesis, pre-scan insertion
• Fastscan (fastscan)
• Scan cell stitching, Test vector generation

5
What this class is about

• Evaluation
• Weekly/Biweekly projects 50
• Weekly Quizzes 15
• Midterm 15
• Final Project 20