WG:1

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MOS-AK Arbeitskreis MOS-Modelle und
Parameterextraktion MOS Modeling and Parameter
Extraction Group
Wladek Grabinski TDL'03, Winthertur, 10 October,
2003
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Outline

• MOS-AK Group
• Brief Group History
• Mission Statement
• MOS-AK and Other Modeling Groups
• MOSFET Standardization Efforts
• MOSFET Modeling Examples

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MOS-AK European Tour Continues
AMS Premstaetten 12/05/95 FH Esslingen
16/02/96 UNI Bremen 22/11/96 BOSCH Reutlinge
n 19/09/97 ELMOS Dortmund
08/05/98 ALCATEL Stuttgart 26/02/99 ZMD Dresd
en 26/11/99 LEG Lausanne
26/05/00 Infineon Munich 05/03/01 AMS Premstaet
ten 19/11/01 MIXDES Wrocalw
20/06/02 Xfab Erfurt 21/10/02 STM Crolles
05/05/03 ESSCIRC Estoril 15/09/03
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MOS-AK Mission Statement

• MOS-AK Connects
• The MOS-AK aims to encourage interaction and
  sharing of all information related to the compact
  modeling at all levels of the device and circuit
  characterization, modeling and simulations. The
  MOS-AK aspires to build a community with global
  connections by
• Promoting standardization of the compact models
  and its implementation into software tools
• Connecting national and local modeling groups on
  European level
• Building strong bilateral ties with similar
  organizations around the world
• MOS-AK Benchmarks
• The MOS-AK conducts regular meetings with
  European industry and academia to exchange
  information on the strengths and weaknesses of
  the industrialization of the compact models.
  Activities include
• Drafting of standards and providing a center of
  competence for engineers, designers, managers and
  decision makers
• Evaluating world-wide best practice and success
  stories
• Delivering a comprehensive view of the European
  compact modeling education
• MOS-AK Educates
• The MOS-AK believes that the transfer of the
  advanced compact modeling methodologies to
  industry can be accelerated by providing the
  comprehensive reports and reference papers on the
  subjects of
• Basic issues and concepts of the device
  characterization and compact modeling
• Global device characterization and compact
  modeling issues

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Modeling Groups and Resources

• CMC Compact Model Council
• CMTC IEEE EDS Compact Modeling Technical
  Committee
• FSA Fabless Semiconductor Association
• ITRS International Technology Roadmap for
  Semiconductors
• NIST National Institute of Standards and
  Technology
• SRC Semiconductor Research Corporation
• Local groups linked to compact modeling
• Analog Design Initiative (ADI)
• Europractice
• Eurotraining
• Microswiss Network

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MOS-AK and CMC
ADMOS Agilent AMD AMS CSEM DAnalyse ELMOS FHG
IMS FHT IHP Infineon LEG-EPFL Mentor
Graphics Motorola Philips Robert Bosch GmbH TEMIC
Semiconductors Silvaco Smart Silicon Systems ST
Microelectronics Uni Bremen ZMD XFab
AMD Agilent Analog Devices Cadence Conexant Hitach
i IBM Infineon Intel Lucent Technologies Mentor
Graphics Motorola NEC Philips ST
Microelectronics TSMC Texas Instruments
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MOS-AK and Japan
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MOS-AK and Japan
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Compact Model StandardizationPresent
ADMOS, Agilent, Danalyse, Gilgamesh, Mentor,
Silvaco, Smart Silicon Systems
CSEM, FHG IMS, FHT, IHP, NTUA, LEG-EPFL
AMD, AMS, Bosch, ELMOS, Infineon, Motorola,
Philips, STM, TEMIC, ZMD, Xemics/ODISS
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Compact Model StandardizationStatus
ADMOS, Agilent, Danalyse, Gilgamesh, Mentor,
Silvaco, Smart Silicon Systems
CSEM, FHG IMS, FHT, IHP, NTUA, LEG-EPFL
AMD, AMS, Bosch, ELMOS, Infineon, Motorola,
Philips, STM, TEMIC, ZMD, Xemics/ODISS
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Compact Model StandardizationFuture
ADMOS, Agilent, Danalyse, Gilgamesh, Mentor,
Silvaco, Smart Silicon Systems
CSEM, FHG IMS, FHT, IHP, NTUA, LEG-EPFL
Model
Verilog-A
AMD, AMS, Bosch, ELMOS, Infineon, Motorola,
Philips, STM, TEMIC, ZMD, Xemics/ODISS
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Benefits Using Verilog-ASM

• For the model developer
• Develop once and run everywhere
• Focus on model equation, not on implementation
• For the software vendors
• Simplified implementation of the standard models
• Proprietary Verilog-A models are also supported
• For the silicon fab
• Standardized model parameter set
• For the end-users (designers)
• Standardized libraries and design kits

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Tools for Compact Model Standardization

• ADMS for Verilog-A defined models
• Laurent Lemaitre
• http//sourceforge.net/projects/mot-adms
• http//sourceforge.net/projects/mot-zspice/
• RTE environment and Verilog-A compiler
• Marek Mierzwinski, Tiburon DA Solution
• http//www.tiburon-da.com

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Alternative Compact MOSFET Models

• Toward sub-100nm MOSFET model for circuit
  simulation that accurately represents new
  physical phenomena
• Quantum Effects
• Modeling of technology fluctuations
• Non quasi static modeling for gt100GHz
• Third generation compact models
• EKV, LEG-EPFL
• HiSIM, Hiroshima University STARC IGFET Model
• MM11, Philips
• SP, PenState, USA

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EKV MOSFET Model

• EKV v2.6 in summary
• a physics based MOSFET model in the public
  domain.
• Design driven modeling concept dedicated to
  analog circuit simulation of submicron CMOS
  circuits.
• used in industrial and academic design groups
• available as Verilog-A and VHDL-AMS code
• on line http//legwww.epfl.ch/ekv/

• EKV v2.6 available in major commercial circuit
  simulators
• ADS, AMI-spice, Antrim-AMS, Aplac, Eldo-Accusim,
  ICCAP, Intosoft, Hsim, LTspice, MacSpice,
  Microsim-CapV, PSpice, NanoSpice, NG-spice,
  Saber, SIMetrix, SmartSpice, Smash, Spice-Opus,
  Spectre, Star-HSpice, Synopsis, Spice3,
  WinSpice.
• on-going implementations
• T-Spice, MINIMOS (TU Vienna), TRANZ-TRAN (TU
  Budapest)

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EKV MOSFET (0.18um CMOS Example)
Drain Current Id
Drain Current Id
Drain Voltage Vd
Drain Voltage Vd
Drain Voltage Vd
Output current Id vs. Vd characteristics
Conductance gds
Conductance gds
Drain Voltage Vd
Drain Voltage Vd
Drain Voltage Vd
Output conductance gds vs. Vd characteristics
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MM11 MOSFET Model

• Suitable for digital, analog and RF
• Suitable for modern/future CMOS processes
• Physics based
• Simulation time comparable to MM9
• Number of parameters comparable to MM9
• Simple parameter extraction
• Implemented physical effects
• mobility reduction
• bias-dependent series resistance
• velocity saturation
• conductance effects (CLM, DIBL, etc.)
• gate leakage current
• gate-induced drain leakage
• gate depletion
• quantum-mechanical effects
• bias-dependent overlap capacitances
• on-line http//www.semiconductors.philips.com/Phi
  lips_Models

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MM11 Model (0.12um CMOS Example)
ID (mA)
ID (mA)
ID (?A)
VDS (V)
VDS (V)
VDS (V)
gDS (A/V)
gDS (A/V)
gDS (A/V)
VDS (V)
VDS (V)
VDS (V)
W/L 10/10?m
W/L 10/0.8?m
W/L 10/0.12?m
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SP - Surface Potential Based Model

• Surface-potential based extrinsic charge model
• Intrinsic charge model is based on DC current
  model
• Analytical approximation for the surface
  potential
• The fs approximation is accurate within 10-8 V
• Symmetric bulk charge linearization
• Bias dependent lateral field gradient factor
• Polysilicon and QM corrections based on surface
  potential and valid in all regions of operation
• Fulfills Gummel symmetry and other benchmarks
• Works for any voltage range from accumulation to
  inversion
• Has been independently verified (Motorola)

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SP HIP6WRF (0.18um CMOS Example)
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Recent Modeling EventMOS-AK/ESSCIRC Workshop

• Y.V. Ponomarev Role of Compact Modeling in
  Scaled CMOS Technologies Development
• L.Lemaitre Software Tools for CM Standardization
• G. Wachutka Coloured Kirchhoffian Networks for
  Multi-Energy and MultiSignal Domain Microsystem
  Models
• S. Cristoloveanu Typical mechanisms in advanced
  SOI MOSFETs and challenging issues for compact
  modeling
• C.Enz, M. Bucher, F. Krummenacher, J.-M. Sallese,
  A.-S. Porret, C. Lallement Charge-Based MOS
  Transistor Modeling in EKV 3.0
• A. J. Scholten, R. van Langevelde, L. F.
  Tiemeijer, R. J. Havens and D.B.M. Klaassen RF
  Applications of MOS Model 11
• M. Sadd and R. Muralidhar Compact Modeling of
  Non-volatile Memory Devices
• A. Laigle, F. Martinez, A. Hoffmann and M.
  Valenza MOSFETs Flicker Noise Modeling For
  Circuit Simulation
• G. Rappitsch Statistical Spice Modeling for
  Analog Circuit Design
• More info http//www.grabinski.ch/mos-ak/

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Summary

• MOS-AK Group was introduced and its European
  activities were presented
• MOS-AK contribution to the compact modeling
  standardization was discussed
• We have also presented
• Tools for compact model standardization
• Alternative compact MOSFET models
• Recent MOS-AK driven modeling event