Processor Core Testing

1
Processor Core Testing

• Aryabartta Sahu
• Entry No 2003 CSZ 0004
• Dept. of Computer Sc. Engg,IITD

2
Outline

• Motivation 1
• Introduction and Definition of Testing
• Different types of simple H/W Testing
  7
• Fault Tolerant Design and Design for Testability
• Testing of Deep submicron ASIC and Processor
• Processor core base design and test
• Instruction Randomization self test 15
• Testing feature and procedure of modern
  processor 1
• Conclusion 1
• References

1
7
15
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1
3
Motivation

• Why testing of Processor ?
• what ever we design should work
  properly .
• we are using verification scheme to
  design properly
• SystemC verification Lib By (Parikshit Patidar
  )
• unfortunately some fabrication error
  occurs in designing the hardware.
• any how final product should work
  properly
• some may bad / good
• Faulty hardware or software may cause valuable
  problems (Reliability)

4
Motivation Contd..

• Testing simple h/w is quite easier .
• Fault like Struck at fault ,Bridging/short
  circuit fault ,stuck-open fault
• Main Difficulty Physical access to internal
  node
• Solution test pattern generation , D algorithm
  , boundary scan ,may be BIST
• What about fault ASIC or Processor ?
• fault may be in any component and
  also multiple fault that may be any type of
  fault
• solution combination of random instruction
  seft test ,s/w base test methodology ,built in
  self test ,boundary scan test
• The advance in Integration scale and
  advance ASIC technology restrict functional test
  (ATGP)
• solution inserting test mechanism in the
  design of flow

5
Introduction
There is no security on the earth, there is only
opportunity Douglas
McArthur (General)
Dependability
Reliability Security
Safety
Design for testability
Diagnosis
Test
Fault-Tolerance BIST Fault Diagnosis Test
6
Introduction Contd ..
How to succeed? Try too
hard! How to fail? Try too
hard! (From American Wisdom)
Cost of quality
Cost
Cost of testing
Cost of the fault
The problem of testing can only be contained not
solved T.Williams
Quality
Optimum test
0
100
7
Introduction Contd ..
Verification vs. Test

• Verifies correctness of manufactured hardware.
• Two-part process
• 1. Test generation software process executed
  once during design
• 2. Test application electrical tests applied to
  hardware
• Test application performed on every manufactured
  device.
• Responsible for quality of devices.

• Verifies correctness of design.
• Performed by simulation, hardware emulation, or
  formal methods.
• Performed once prior to manufacturing.
• Responsible for quality of design.

8
Introduction Contd ..

• History of Testing
• 1960s Racks ? Functional testing
• 1970s Boards ? Structural testing
• Complexities, automata,
• 1980s VLSI ? Design for testability (DFT)
• Interactivity vs. testability?
  Hierarchy top-down, bottom-up
• 1990s VLSI ? Self-test, Fault-tolerance
• Testability, Boundary-scan standard
• 2000s Systems on Chip (SoC) ? Built-in
  Self-Test (BIST)

9
Fault in Digital Circuit

• Bridging / short-circuit fault (input are short )
• Struck open Fault (some portion open in the
  circuit )
• Struck at Fault (sa0,sa1)
• Temporary fault (active due to noise or temp)

10
Basics of Theory for Test

• Two basic tasks
• Which test patterns are needed to detect a fault
  (or all faults)
• 2. Which faults are detected by a given test (or
  by all tests)

11
Test Pattern Generation

• Test Pattern for combinational circuit
• One Dimensional path Sensitization
• Boolean Difference
• D-Algorithm
• Path Oriented Decision Making (PODEM)
• Test Pattern Generation in Sequential circuit
• Testing SC and iterative CC
• State Table verification
• Random testing
• Scan based testing
• Signature Analysis

12
Problems of Ideal Tests using Test Pattern

• Ideal tests detect all defects produced in the
  manufacturing process.
• Ideal tests pass all functionally good devices.
• Very large numbers and varieties of possible
  defects need to be tested.
• Difficult to generate tests for some real
  defects. Defect-oriented testing is an open
  problem.

13
Fault Tolerant Design of Digital System
(Redundancy)

• Redundant hardware are fault tolerant
• Static Redundancy
• Triple Modular redundancy
• Error correcting code
• Dynamic Redundancy
• Hybrid Redundancy
• In Memory redundant Error Correcting Code used
• Time Redundancy
• Software Redundancy in Co-design environment.

14
Design for Testabilty

• Testability ,Controllability Observability
• Testable design of Combinational Circuit
• Reed-Muller expansion Technique
• Use of Control logic
• Testable Design of Sequential circuit
• Scan Path Technique
• Level Sensitive Scan Design (LSSD)
• Random Access Scan Technique (RAST)
• Built in Self Test (BIST ) generally used in
  processor testing

15
Types of Testing

• Verification testing, characterization testing,
  or design debug
• Verifies correctness of design and of test
  procedure usually requires correction to design
• Manufacturing testing
• Factory testing of all manufactured chips for
  parametric faults and for random defects
• Acceptance testing (incoming inspection)
• User (customer) tests purchased parts to ensure
  quality

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Manufacturing Test

• Determines whether manufactured chip meets specs
• Must cover high of modeled faults
• Must minimize test time (to control cost)
• No fault diagnosis
• Tests every device on chip
• Test at speed of application or speed guaranteed
  by supplier

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Burn-in or Stress Test

• Process
• Subject chips to high temperature over-voltage
  supply, while running production tests
• Catches
• Infant mortality cases these are damaged chips
  that will fail in the first 2 days of operation
  causes bad devices to actually fail before chips
  are shipped to customers
• Freak failures devices having same failure
  mechanisms as reliable devices

18
Costs of Testing

• Design for testability (DFT)
• Chip area overhead and yield reduction
• Performance overhead
• Software processes of test
• Test generation and fault simulation
• Test programming and debugging
• Manufacturing test
• Automatic test equipment (ATE) capital cost
• Test center operational cost

19
Testability feature in processor core base
design

• Presently Most new Design is Using Complex Core
  rather then standard cell and macro-blocks
• Processor Core Classification (Cube of processor
  core)
• Processor available as
• Domain specific features
• Application specific feature
• Testing using
• Boundary Scan
• In-circuit emulation (ICE)
• BIST and Software Testing

20
Built-In Self-Test

• Motivations for BIST
• Need for a cost-efficient testing
• Doubts about the stuck-at fault model
• Increasing difficulties with TPG (Test Pattern
  Generation)
• Growing volume of test pattern data
• Cost of ATE (Automatic Test Equipment)
• Test application time
• Gap between tester and UUT (Unit Under Test)
  speeds
• Drawbacks of BIST
• Additional pins and silicon area needed
• Decreased reliability due to increased silicon
  area
• Performance impact due to additional circuitry
• Additional design time and cost

21
Built-In Self-Test
System-on-Chip

• Advances in microelectronics technology have
  introduced a new paradigm in IC design
  System-on-Chip (SoC)
• Many systems are nowadays designed by embedding
  predesigned and preverified complex functional
  blocks (cores) into one single die
• Such a design style allows designers to reuse
  previous designs and will lead to shorter
  time-to-market and reduced cost

22
Built-In Self-Test
System-on-Chip testing

• Test architecture components
• Test pattern source sink
• Test Access Mechanism
• Core test wrapper

• Solutions
• Off-chip solution
• need for external ATE
• Combined solution
• mostly on-chip, ATE needed for control
• On-chip solution
• BIST

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Built-In Self-Test

• BIST components
• Test pattern generator (TPG)
• Test response analyzer (TRA)
• TPG TRA are usually implemented as linear
  feedback shift registers (LFSR)
• Two widespread schemes
• test-per-scan
• test-per-clock

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Built-In Self-Test
Test per Scan
Initial test set T1 1100 T2 1010 T3 0101 T4
1001 Test application 1100 T 1010 T 0101T 1001
T Number of clocks 4 x 4 4 20

• Assumes existing scan architecture
• Drawback
• Long test application time

25
Built-In Self-Test
Test per Clock

• Initial test set
• T1 1100
• T2 1010
• T3 0101
• T4 1001
• Test application
• 1 10 0 1 0 1 0 01 01 1001
• T1 T4 T3 T2
• Number of clocks 10

Combinational Circuit Under Test
Scan-Path Register
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Built-In Self-Test
Test per Clock
BILBO - Built- In Logic Block Observer
CSTP - Circular Self-Test Path
LFSR - Test Pattern Generator
LFSR - Test Pattern Generator Signature
analyser
Combinational circuit
Combinational circuit
LFSR - Signature analyzer
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Built-In Self-Test

• Pseudorandom Test generation by LFSR

• Using special LFSR registers
• Several proposals
• BILBO
• CSTP
• Main characteristics of LFSR
• polynomial
• initial state
• test length

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Pseudorandom Test Generation

• LFSR Linear Feedback Shift Register

Standard LFSR
1
x
x2
x4
x3
Modular LFSR
x4
x2
x
1
x3
Polynomial P(x) 1 x3 x4
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Cube of Processor types
Processor available as
Application specific feature
ASIP
package
DSP
Possible (ASIP)
CORE
Core CAD cell
For DSP
None general purpose architecture
Domain specific feature
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Testability feature in ASIC and Processor core
base design

• In some case ASIC integrated with processor core
  (Ex DSP) Example Voice Decoder ASIC in
  military application

Emulation Test port
IEEE1149.1 Test access port
External CLK
External program memory
PPL
DSP core
JTAG Controller
Program ROM
CLOCK generation
Host Interface
Auto Gain Control
Data Memory
Serial Port
From/to CODEC
From/to Controller
Ex AGC
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Testability feature in ASIC and processor core
base design

• Each component have BIST and finally its
  interfaced with the IEEE 1149.1 Test access port

Microc Bus
IEEE 1149.1 bus
IEE 1149.1 TAP
Host Interface
intest
signature
Program Memory
DSP CORE
MISR
Test Pattern
Test response
DSP BIST
ROM BIST
RAM BIS
Register BIST
Logic BIST
Intrf BIST
Data RAM
Clock Gen
Serial Int
Coff ROM
Host Interface
DSP core
PLL
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Test Algorithm of previous BIST Architecture
BEGIN
Reset of the MISR
Test Algorithm BIST
Save the signature
Signature Expected value
Set Flag OK
Set flag NOK
Return
33
Testability feature in ASIC and Processor core
base design

• Boundary scan Model for testing
• Standardized language Boundary scan Description
  Language
• Introduction of boundary scan circuitry into ASIC
  
• Boundary Scan Model and HDL can be done together
  to get the final netlist
• Validation of BSDL model used for generation of
  Test pattern and
• test response from Validation (Ex Victory TM
  )

34
BSDL and Boundary Scan Validation Flow
BSDL MODEL
BSDL Validation Ex By Victory TM
Boundary scan logic capture
Test Patterns
Test Responses
HDL Test Bench
Boundary scan HDL Netlist
HDL Simulation
Simulation Responses
Comparison
NOT Ok
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Boundary Scan test result Using the BSDL

• Voice Decoder ASIC fault grade

36
Instruction Randomization self test (IRST )

• Scan base testing method can t be applied to P
  core , which can not be modified to meet the
  design requirements of scan Insertion
• IRST exploits functional behavior of micro
  processor to achieves stuck_at-fault converge
  with out scan insertion and MUX isolation of
  application of test pattern
• New BIST which combines execution of instructions
  with a small amount of on chip test h/w which is
  used to randomize those instructions
• IRST well suited for meeting challenges of
  testing ASIC which contain embedded processor
  core

37
Instruction Randomization self test (IRST ) contd
..

• Testing is done by continuously executing a
  random stream of processor instructions and
  compressing execution result using internal test
  hardware.
• Special software program written in native
  assembler code of processor, are designed to
  exploit the randomization behavior to achieve the
  observability and controllability need for good
  fault coverage .
• Generally fault validation in gate level But in
  IRST approaches in RTL level abstracting gate
  level and focusing on functional and Instruction
  level behavior of processor
• Instruction level coverage along with
  randomization make efficient and effective test

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IRST Architecture
Key component of IRST is Test software and Test
hardware
Test Software reside in internal Memory
Test hardware
Randomize software Program
Provide controllability over processor logic
,make processor behavior visible
Observes Processor logic to detect Fault
Processor Core
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IRST test hardware

• Provides
• Modifies test software to provide a pseudo random
  sequence of instructions , thus creating a
  randomized test program
• Monitor the Inst-fetch and R/W activity as the
  test s/w execute to determine if the behavior
  indicate s faulty logic
• A sources of randomized seed data which the test
  s/w uses to randomized the register operand .
• Consist of
• Modifiable instruction storage( MIS)
• Fixed test instructions Memory (FTI )
• Randomizer
• A Test response Compression device (TRCD )

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IRST test hardware Contd
MIS Memory RAM
FTI Memory ROM
TRCD
Memory ctl signal
Random data
Randomizer
Common I/O bus
Processor Core
41
IRST test hardware Contd

• IRST is most cost effective if embedded RAM
  already exist
• IRST is like a BIST test method code store must
  exist in ASIC
• Observability of core provided by TRCD which is a
  Linear Feedback Shift Register (LFSR )
  configured as CRC generator
• TRCD used for observe and compress signals into a
  repeatable signature .

42
IRST test Software

• Provides
• Source of random stimulus for controllability
  over various data and control paths in the
  processor as random instruction execute
• Accomplish with assistance of hard ware
  randomizer which control the test software giving
  stochastic behavior that enough to test the
  processor logic
• Some structure must be given to the software so
  that Others function can also do during test
• Obsevability of internal registers
• Randomization of instruction operand
• Determination of test completion
• IRST pass/fail criteria condition

43
IRST test result

• SA 0/1 Fault coverage about 92.5 after
  third test
• Up to 94.8 percent of fault coverage achieved
  after more test

44
Testing feature and procedure of modern processor

• PII,PIII, PIV
• Built-in Self Test (BIST) Provides single
  stuck-at fault coverage of the microcode and
  large logic arrays, plus testing of the
  instruction cache, data cache, Translation
  Lookaside Buffers, and ROMs
• IEEE 1149.1 Standard Test Access Port and
  Boundary Scan Enables testing of the Pentium
• XEON
• Features Used for Testing and Performance /
  Thermal Monitoring
• IEEE 1149.1 Standard Test Access Port and
  Boundary Scan mechanism enables testing of the
  Intel Xeon processor and system connections
  through a standard interface.
• Includes a new on-die Thermal Control Circuit
  that allows motherboards to be cost effectively
  designed to expected application power usages
  rather than theoretical maximums.

45
Conclusion

• hard ware testing is a separate and vast area
• We can t guarantee 100 fault free after
  several test also. But tried maximize fault
  coverage
• Very deep submicron ASIC ,ASIP and processor are
  generally use combination of all type of testing
  (boundary scan ,BIST,Software base test ).
• At time of design of system we have think about
  the testing .

46
References

• Parag K. lala Fault Tolerant and Fault
  Testable Hardware Design BS publication
• F pichon Testability feature of submicron Voice
  coder ASIC IEEE 0-7803-3540-6 6/96
• Peter Marwedel Processor -Core Based test and
  test IEEE 1997 ,0-7803-3662-3/97
• Ken Batcher ,Christos papachristou Instruction
  Randomisation Self test for Processor core IEEE
  vol 6/1999 ,0-7803-3663-4/1999
• Yervant Zorian ,Sujit dey ,Michel J Rodgers Test
  of Future System on chips IEEE 0-7803-6445
  -7/00 2000
• www.intel.com