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CS2100 Computer Organisationhttp//www.comp.nus.e
du.sg/cs2100/

• MIPS Introduction
• (AY2008/9) Semester 2

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WHERE ARE WE NOW?

• Number systems and codes
• Boolean algebra
• Logic gates and circuits
• Simplification
• Combinational circuits
• Sequential circuits
• Performance
• Assembly language
• The processor Datapath and control
• Pipelining
• Memory hierarchy Cache
• Input/output

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MIPS INTRODUCTION

• Instruction Set Architecture
• RISC vs CISC
• Instruction Set Architecture Concepts
• Simple MIPS Instructions
• Addition
• Subtraction
• Constant/Immediate Operands
• Register Zero
• Logical Operations

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RECAP BELOW YOUR PROGRAM

• You write programs in high level programming
  languages, e.g., C, Java
• AB
• Compiler translates this into assembly language
  statement
• add A,B
• Assembler translates this statement into machine
  language instructions that the processor can
  execute
• 1000110010100000

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RECAP INSTRUCTION EXECUTION CYCLE

• Instruction execution cycle fetch, decode,
  execute.
• Fetch fetch next instruction (using PC) from
  memory into IR.
• Decode decode the instruction.
• Execute execute instruction.

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INSTRUCTION SET ARCHITECTURE (1/5)

• Instruction Set Architecture (ISA) an
  abstraction on the interface between the hardware
  and the low-level software.

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INSTRUCTION SET ARCHITECTURE (2/5)

• The ISA includes everything programmers need to
  know to make the machine code work correctly.
• It allows computer designers to talk about
  functions independently from the hardware that
  performs them.
• This abstraction allows many implementations of
  varying cost and performance to run identical
  software.
• Example Intel x86/IA-32 ISA has been implemented
  by a range of processors starting from 80386
  1985 to Pentium 4 2005
• Other companies such as AMD and Transmeta have
  implemented IA-32 ISA as well
• A program compiled for IA-32 ISA can execute on
  any of these implementations

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INSTRUCTION SET ARCHITECTURE (3/5)

• ISA is determined by
• Organization of programmable storage.
• Data types and data structures encoding and
  representations.
• Instruction formats.
• Instruction (or operation code, opcode) set.
• Modes of addressing and accessing data items and
  instructions.
• Exceptional conditions.

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INSTRUCTION SET ARCHITECTURE (4/5)

• Instruction format or encoding
• how is it decoded?
• Location of operands and result
• where other than memory?
• how many explicit operands?
• how are memory operands located?
• which can or cannot be in memory?
• Data type and size
• Operations
• what are supported?
• Successor instruction
• jumps, conditions, branches
• Fetch-decode-execute is always done for any
  instruction!

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INSTRUCTION SET ARCHITECTURE (5/5)

• Instruction set language of the machine.
• More primitive than high-level languages (eg no
  sophisticated control flow).
• More restrictive instructions.
• We will study MIPS instruction set, used by NEC,
  Nintendo, Silicon Graphics, Sony.

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ASSEMBLY LANGUAGE

• Machine code
• Instructions are represented in binary
• 1000110010100000 is an instruction that tells one
  computer to add two numbers
• Hard and tedious for programmer
• Assembly language
• Symbolic version of machine code
• Human readable
• add A, B is equivalent to 1000110010100000
• Assembler translates from assembly language to
  machine code
• Assembly can provide pseudo-instructions.
  Example In MIPS, move t0, t1 is a
  pseudo-instructions the actual instruction is
  add t0, t1, zero.
• When considering performance, only real
  instructions are counted.

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RISC VERSUS CISC

• Complex Instruction Set Computer (CISC) e.g. x86
• Single instruction performs complex operation
• VAX architecture had an instruction to multiply
  polynomials
• Smaller program size as memory was premium
• Complex implementation, no room for hardware
  optimization
• Reduced Instruction Set Computer (RISC) e.g. MIPS
• Keep the instruction set small and simple, makes
  it easier to build/optimize hardware
• Burden on software to combine simpler operations
  to implement high-level language statements
• Pentium 4 decomposes many x86 instructions into a
  series of internal micro-operations that are
  executed by the processor core
• CISC ISA but internal RISC implementation

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CONCEPT 1 DATA STORAGE

• Memory Organization
• Storage Architecture
• Registers

Concept 1 Data Storage Concept 2 Memory
Addressing Modes Concept 3 Operations in the
Instruction Set Concept 4 Instruction
Formats Concept 5 Encoding the Instruction
Set Concept 6 Compilers View
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MEMORY ORGANIZATION (1/2)

• The main memory can be viewed as a large,
  single-dimension array of memory locations.
• Each location of the memory has an address, which
  is an index into the array.
• The memory map on the right contains one byte (8
  bits) in every location/address.
• Byte addressing means the index points to a byte
  of memory.
• Word addressing see next slide.

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MEMORY ORGANIZATION (2/2)

• A word is unit of transfer between processor and
  memory.
• Assuming 4-byte words and n-bit address.
• 2n bytes with byte addresses from 0 to 2n 1.
• 2n-2 words with byte addresses 0, 4, 8, , 2n
  4.
• Words are aligned.
• What are the last two bits of the address of a
  word, if each word contains 4 bytes? Answer

?
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STORAGE ARCHITECTURE (1/4)
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STORAGE ARCHITECTURE(2/4)

• Stack architecture Operands are implicitly on
  top of the stack.
• Accumulator architecture One operand is
  implicitly in the accumulator (a register).
  Examples IBM 701, DEC PDP-8.
• General-purpose register architecture Only
  explicit operands.
• Register-memory architecture (one operand in
  memory). Examples Motorola 68000, Intel 80386.
• Register-register (or load-store) architecture.
  Examples MIPS, DEC Alpha.
• Memory-memory architecture All operands in
  memory. Example DEC VAX.

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STORAGE ARCHITECTURE(3/4)
CAB
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STORAGE ARCHITECTURE(4/4)

• The following shows the compilation of the
  statement A BC in different architectures.
• Stack architecturepush AddrC TopTop4
  StackTopMemoryAddrCpush AddrB TopTop4
  StackTopMemoryAddrBadd
  StackTop-4StackTopStackTop-4
  TopTop-4pop AddrA MemoryAddrAStackTop
  TopTop-4
• Accumulator architecture load AddrB Acc
  MemoryAddrB, or Acc Badd AddrC Acc B
  MemoryAddrC, or Acc B Cstore AddrA
  MemoryAddrA Acc, or A B C
• Memory-memoryadd AddrA, AddrB, AddrC

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REGISTERS (1/3)

• Fast memories in the processor.
• Data are transferred from memory to registers for
  faster processing.
• Compiler associates variables in program with
  registers. (What about programs with many
  variables?)
• Registers have no type, unlike variables.
• Code density improves.
• Modern architectures predominantly use the
  load-store register architecture.
• Limited in number. A typical system has 16 to 32
  registers.

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REGISTERS (2/3)

• MIPS assembly language 32 registers, referred to
  by a number (0, 1, , 31) or a name (eg a0,
  t1).

at (register 1) is reserved for the
assembler. k0-k1 (registers 26-27) are reserved
for the operation system.
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REGISTERS (3/3)

• Classifying general-purpose register computers
• ALU (Arithmetic-Logic Unit) instruction has two
  or three operands?
• Add R2, R1 (R2R2R1) or Add R3, R2, R1
  (R3R2R1)
• How many operands may be memory addresses in an
  ALU instruction?
• Zero? One? Two? Three?
• What are the advantages and disadvantages of each
  of these options?

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CONCEPT 2 MEMORY ADDRESSING MODE

• Memory Locations and Addresses
• Memory Operations
• Addressing Modes

Concept 1 Data Storage Concept 2 Memory
Addressing Modes Concept 3 Operations in the
Instruction Set Concept 4 Instruction
Formats Concept 5 Encoding the Instruction
Set Concept 6 Compilers View
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MEMORY LOCATIONS AND ADDRESSES (1/3)

• Memory is viewed as a large one-dimensional array
  of bits.
• Group of n bits to store or retrieve in a single
  operation to/from the memory is a word.
• A word is usually a multiple of bytes and
  typically 2, 4 or 8 bytes.
• Memory is addressed to access a single word or a
  byte using a distinct address.
• Given k-bit address, the address space is of size
  2k.
• 24-bit address generates 224 ( 16,777,216)
  addresses or locations. This is 16M.

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MEMORY LOCATIONS AND ADDRESSES (2/3)

• Byte addressability Successive memory addresses
  refer to successive byte locations in the memory.
• Big-endian most significant byte stored in
  lowest address.
• IBM 360/370, Motorola 68000, MIPS (Silicon
  Graphics), SPARC.
• Little-endian least significant byte stored in
  lowest address.
• Intel 80x86, DEC VAX, DEC Alpha.

Example 0xDEADBEEF
Big-endian Most significant byte first DE AD BE
EF. Little-endian Least significant byte first
EF BE AD DE.
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MEMORY LOCATIONS AND ADDRESSES (3/3)

• Word alignment Words are aligned in memory if
  they begin at a byte address that is a multiple
  of the number of bytes in a word.

Example If a word consists of 4 bytes, then
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MEMORY OPERATIONS (1/2)

• Load (Read) Transfers the contents of a specific
  memory location to the processor. The processor
  sends address to the memory, and the memory reads
  data at that address and sends to processor.
• Store (Write) Data from the processor is written
  at a specified memory location. Processor sends
  address and data to the memory.

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MEMORY OPERATIONS (2/2)
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ADDRESSING MODES
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MIPS ADDRESSING MODES (1/4)

• Register (direct) mode

op opcode rs first source register rt second
source register rd destination register
Example add r3, r1, r2
Note For illustration only. This is not the
exact MIPS syntax.
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MIPS ADDRESSING MODES (2/4)

• Immediate mode

op opcode rs source register rt destination
register immed constant
Example addi r3, r1, 12
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MIPS ADDRESSING MODES (3/4)

• Displacement mode (base addressing)

Example lw r1, 100(r2)
r2 150 100(r2) 88
Address 250
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MIPS ADDRESSING MODES (4/4)

• PC-relative mode

Example beq r1, r2, 6
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CONCEPT 3 OPERATIONS IN THE INSTRUCTION SET

• Standard Operations in an Instruction Set
• Frequently Used Instructions
• Instructions for Control Flow

Concept 1 Data Storage Concept 2 Memory
Addressing Modes Concept 3 Operations in the
Instruction Set Concept 4 Instruction
Formats Concept 5 Encoding the Instruction
Set Concept 6 Compilers View
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STANDARD OPERATIONS
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FREQUENTLY USED INSTRUCTIONS
Make these instructions fast! Amdahls law make
the common case fast!
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INSTRUCTIONS FOR CONTROL FLOW

• Branch conditional (if ltconditiongt go to
  ltaddressgt)
• Jump unconditional (go to ltaddressgt)
• Procedure calls/returns
• Addressing modes for control-flow instructions
• PC-relative destination address displacement
  value in PC(When target address is near the
  current instruction, it requires only a few bit.
  Code can run independently of where it is loaded
  position independence.)
• Register indirect jumps a register is specified,
  which will contain the target address.(Value in
  the specified register is usually not known at
  compile time, but is computed at run time.)

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CONCEPT 4 INSTRUCTION FORMATS

• Instruction Length
• Instruction Fields
• Type and Size of Operands

Concept 1 Data Storage Concept 2 Memory
Addressing Modes Concept 3 Operations in the
Instruction Set Concept 4 Instruction
Formats Concept 5 Encoding the Instruction
Set Concept 6 Compilers View
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INSTRUCTION LENGTH

• Variable-length instructions.
• Intel 80x86 Instructions vary from 1 to 17 bytes
  long.
• Digital VAX Instructions vary from 1 to 54 bytes
  long.
• Require multi-step fetch and decode.
• Allow for a more flexible (but complex) and
  compact instruction set.

• Fixed-length instructions.
• Used in most RISC (Reduced Instruction Set
  Computers)
• MIPS, PowerPC Instructions are 4 bytes long.
• Allow for easy fetch and decode.
• Simply pipelining and parallelism.
• Instruction bits are scarce.
• Hybrid instructions a mix of variable- and
  fixed-length instructions.

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INSTRUCTION FIELDS

• An instruction consists of opcode and a certain
  number (possible zero) of operands.
• Each instruction has a unique opcode, but
• How many operands?
• Are the operands registers or memory?
• Current high-end processors allow for three
  register operands.
• Hence if there are 32 registers, then 3 x 5 15
  bits are used up for the operands.
• For every direct memory operand, at least one
  operand will be taken away.
• Example LOAD/STORE instructions only have two
  operands.

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TYPE AND SIZE OF OPERANDS

• Encoding in the opcode designates the type of an
  operand.
• Add R3, R2, R1
• Character (8 bits), half-word (eg 16 bits), word
  (eg 32 bits), single-precision floating point
  (eg 1 word), double-precision floating point
  (eg 2 words).
• Expectations from any new 32-bit architecture
• Support for 8-, 16- and 32-bit integer and 32-bit
  and 64-bit floating point operations. A 64-bit
  architecture would need to support 64-bit
  integers as well.

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CONCEPT 5 ENCODING THE INSTRUCTION SET

• Instruction Encoding
• Encoding for Fixed-Length Instructions

Concept 1 Data Storage Concept 2 Memory
Addressing Modes Concept 3 Operations in the
Instruction Set Concept 4 Instruction
Formats Concept 5 Encoding the Instruction
Set Concept 6 Compilers View
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INSTRUCTION ENCODING (1/2)

• How are instructions represented in binary format
  for execution by the processor?
• Issues
• Code size, speed/performance, design complexity.
• Things to be decided
• Number of registers
• Number of addressing modes
• Number of operands in an instruction
• The different competing forces
• Have many registers and addressing modes
• Reduce code size
• Have instruction length that is easy to handle
  (fixed-length instructions are easy to handle)

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INSTRUCTION ENCODING (2/2)

• Three encoding choices variable, fixed, hybrid.

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ENCODING FOR FIXED-LENGTH INSTRUCTIONS (1/4)

• How to fit multiple sets of instruction types
  into a fixed-length instruction format? Work out
  the most constrained set first.
• An expanding opcode scheme is one where the
  opcode has variable lengths for different
  instructions. This maximizes the instruction
  bits.
• Example Given a fixed-length instruction set
  where each instruction contains 16 bits. Some
  instructions (call it type-A) require 2 operands,
  while other instructions (call it type-B) require
  only 1 operand. Each operand takes up 5 bits.

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ENCODING FOR FIXED-LENGTH INSTRUCTIONS (2/4)

• If we assume the all opcodes must have the same
  size, to allow for the maximum number of
  instructions, the opcodes must be 6 bits long.

• We see that there are wasted bits, and the
  maximum total number of instructions is 26 or 64.

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ENCODING FOR FIXED-LENGTH INSTRUCTIONS (3/4)

• If we allow the opcode for type-B instructions to
  be 11 bits long, we may have a bigger set of
  instructions.

• This is known as expanding opcode.
• Encoding concern The first 6 bits of the opcode
  for any type-B instruction must not be identical
  to the opcode of any of the type-A instructions.
  (Why?)

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ENCODING FOR FIXED-LENGTH INSTRUCTIONS (4/4)

• What is the maximum total number of instructions
  possible?

• Answer 1 (26 1) ? 25 1 63?32 2017.
• How? Let there be 1 type-A instruction (assume
  the opcode is 000000 the choice is arbitrary),
  then there are (26 1) valid patterns for the
  first 6 bits of the type-B instructions, followed
  by any 5 bits.

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EXAMPLE

• Design an expanding opcode for the following to
  be encoded in a 36-bit instruction format. An
  address takes up 15 bits and a register number 3
  bits.
• 7 instructions with two addresses and one
  register number.
• 500 instructions with one address and one
  register number.
• 50 instructions with no address or register.

One possible answer
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QUESTIONS (1/2)

• A certain machine has 12-bit instructions and
  4-bit addresses. Some instructions have one
  address and others have two. Both types of
  instructions exist in the machine.

• What is the maximum number of instructions with
  one address?
• 15
• 16
• 240
• 256
• None of the above

?
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QUESTIONS (2/2)

• What is the mimimum total number of instructions,
  assuming the encoding space is completely
  utilized (that is, no more instructions can be
  accommodated)?
• 31
• 32
• 48
• 256
• None of the above

?
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CONCEPT 6 COMPILERS VIEW

• Considerations for Compiler

Concept 1 Data Storage Concept 2 Memory
Addressing Modes Concept 3 Operations in the
Instruction Set Concept 4 Instruction
Formats Concept 5 Encoding the Instruction
Set Concept 6 Compilers View
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CONSIDERATIONS FOR COMPILER

• Ease of compilation.
• Orthogonality no special registers, few special
  cases, all operand modes available with any data
  type or instruction type.
• Completeness support for a wide range of
  operations and target applications.
• Regularity no overloading for the meanings of
  instruction fields.
• Streamlined resource needs easily determined.
• Provide at least 16 general-purpose registers
  plus separate floating-point registers.
• Be sure all addressing modes apply to all data
  transfer instructions.
• Aim for a minimalist instruction set.

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MIPS ASSEMBLY LANGUAGE

• In MIPS assembly language, each instruction
  executes a simple command
• Each line of assembly code contains at most 1
  instruction
• Instructions are related to operations (, -, ,
  /, ) in C/Java
• is used for comments
• Anything from mark to end of line is a comment
  and will be ignored

add t0, s1, s2 tmp b c sub s0, t0,
s3 a tmp - d
Acknowledgement The slides starting from here
are taken from Dr Tulikas CS1104 materials.
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ARITHMETIC ADDITION

• Addition in assembly
• C a b c
• MIPS add s0, s1, s2
• s0 ? variable a
• s1 ? variable b
• s2 ? variable c
• Natural number of operands for an instruction is
  3 (2 sources 1 destination)
• Why?
• Keep the hardware simple
• Design principle Simplicity favors regularity

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INSTRUCTION SYNTAX

• add s0, s1, s2

s0 s1 s2
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RECALL MIPS REGISTERS

• MIPS assembly language 32 registers, referred to
  by a number (0, 1, , 31) or a name (eg a0,
  t1).

at (register 1) is reserved for the
assembler. k0-k1 (registers 26-27) are reserved
for the operation system.
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ARITHMETIC SUBTRACTION

• Subtraction in assembly
• C a b c
• MIPS sub s0, s1, s2
• s0 ? variable a
• s1 ? variable b
• s2 ? variable c
• Positions of s1 and s2 (i.e., source1 and
  source2) are important for subtraction

s0 s1 - s2
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COMPLEX STATEMENTS (1/2)

• C statement
• a b c - d
• A single instruction can handle at most two
  source operands.
• Break it up into multiple instructions and use
  temporary register t0 t7
• add t0, s1, s2 tmp b c
• sub s0, t0, s3 a tmp - d
• A single line of C statement may break up into
  several lines of MIPS assembly
• Who is doing this break up when you write
  high-level language code?

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COMPLEX STATEMENTS (2/2)

• C statement
• f (g h) (i j)
• Break it up into multiple instructions
• Replace variables by registers s0 s7
• Use two temporary registers t0, t1
• add t0, s1, s2 tmp0 g h
• add t1, s3, s4 tmp1 i j
• sub s0, t0, t1 a tmp0 tmp1

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TRY IT YOURSELF

• z a b c d
• as0 bs1 cs2 ds3 zs4
• z (a b) c
• as0 bs1 cs2 zs4

?
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CONSTANT/IMMEDIATE OPERANDS

• Immediates are numerical constants
• They appear often in operations so there is
  special instruction for them
• Add immediate (addi)
• C a a 4
• MIPS addi s0, s0, 4 s0 s0 4
• Syntax is similar to add instruction but source2
  is a constant instead of register
• Design principle Make common case fast
• No subi instruction in MIPS why?

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REGISTER ZERO

• One particular immediate, the number zero (0),
  appears very often in code
• Define register zero (0 or zero) to always have
  the value 0
• C f g
• MIPS add s0, s1, zero
• where MIPS registers s0 and s1 are associated
  with variables f and g
• This instruction
• add zero, zero, s0
• does not do anything!

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LOGICAL OPERATIONS

• Arithmetic instructions view content of a
  register as a single quantity (signed or unsigned
  integer)
• New perspective View register as 32 raw bits
  rather than as a single 32-bit number
• Consequence Useful to operate on individual
  bytes or bits within a word

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SHIFT INSTRUCTIONS (1/2)

• Opcode sll (shift left logical)
• Move all the bits in a word to the left by a
  number of bits fill the emptied bits with zeroes
• Example register s0 contains0000 1000 0000
  0000 0000 0000 0000 1001 sll t2, s0, 4 t2
  s0ltlt4shifts left by 4 bits results in content
  of register t21000 0000 0000 0000 0000 0000
  1001 0000

• Q Shifting left by n bits gives the same result
  as multiplying by what value? Answer

?
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SHIFT INSTRUCTIONS (2/2)

• Opcode srl (shift right logical)
• Shifts right and fills emptied bits with zeroes
• Q Shifting right by n bits is the same as what
  mathematical operation? Answer
• Shifting is faster than multiplication/division
• Good compiler translates such multiplication/divis
  ion into shift instructions
• C a a 8MIPS sll s0, s0, 3

?
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BITWISE AND INSTRUCTION (1/2)

• AND bitwise operation that leaves a 1 only if
  both the bits of the operands are 1
• Example and t0, t1, t2t1 0000 0000 0000
  0000 0000 1101 0000 0000t2 0000 0000 0000 0000
  0011 1100 0000 0000t0 0000 0000 0000 0000 0000
  1100 0000 0000

• AND can be used to create a mask. Force 0s into
  the positions that you are not interested other
  bits will remain the same as the original.

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BITWISE AND INSTRUCTION (1/2)

• Example andi t0, t1, 0xFFFt1 0000 1001
  1100 0011 0101 1101 1001 11000xFFF 0000 0000
  0000 0000 0000 1111 1111 1111t0
• In the above example we are interested in the
  last 12 bits of the word in register t1. So we
  use 0xFFF as the mask.

?
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BITWISE OR INSTRUCTION

• OR bitwise operation that places a 1 in the
  result if either operand bit is 1
• Can be used to force certain bits to 1s
• Example ori t0, t1, 0xFFFt1 0000 1001
  1100 0011 0101 1101 1001 1100OxFFF 0000 0000
  0000 0000 0000 1111 1111 1111t0
• If both operands are registers then use or
• Example or t0, t1, t2

?
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BITWISE NOR INSTRUCTION

• Required operation is NOT toggles the bits of an
  operand (1 with 0, 0 with 1)
• To maintain regularity (simplicity favors
  regularity), MIPS uses NOR instead of NOT
• If one operand of NOR is 0, then it is equivalent
  to NOT A NOR 0 NOT(A OR 0) NOT(A)
• Example nor t0, t1, zero
• t1 0000 1001 1100 0011 0101 1101 1001 1100
• t0
• There is no nori in MIPS why?

?
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READING ASSIGNMENT

• Instructions Language of the Computer
• COD Chapter 2, pg 46-53, 58-71. (3rd edition)
• COD Chapter 2, pg 74-81, 86-87, 94-104. (4th
  edition)

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END