Preemptive Scheduling and Mutual Exclusion with Hardware Support

1
Preemptive Scheduling andMutual Exclusion with
Hardware Support

• Vivek Pai / Kai Li
• Princeton University

2
Mechanics

• Reading up to and including 2.2.5
• Also read Lamports paper
• Project 2 handouts
• Format for design reviews?
• Any feedback?

3
The Hello/Goodbye Server

• Server Hello
• User Hello
• Server Drink Slurm! (ka-ching!)
• User Goodbye
• Server Goodbye

4
Life is Simple Until

• Hello,
• My name is Bill Gates. Please try out my new
  Hello/Goodbye Server and Ill give you a
  million dollars and a new cat. Tell your friends.
• I wuv you,
• Bill Gates

5
You Have to Fix It

• accept new connection say hello
• wait for hello print advertising message
• wait for goodbye, say goodbye
• close connection

6
Whats the Simplest Option?

• While (1)
• accept new connection
• fork new process
• let process handle connection
• Drawback lots of process creation/deletion

7
Can We Reduce Forks?

• At program launch, fork some number
• While (1)
• accept
• wait for hello
• wait for goodbye
• close

8
Can We Use Threads?

• At program launch, start some threads
• While (1)
• accept connection
• wait for hello
• wait for goodbye
• close

T2
T1
9
Signals and Interrupts

• Both are asynchronous
• Used to notify system of event occurrence
• Signal delivered by OS to process
• Interrupt delivered by hardware to OS
• Some overlap/interaction? Definitely
• Examples?
• Code tries executing divide-by-zero
• User disconnects (hangs up)

10
I/O and Timer Interrupts

• Why
• Timer interrupt to do CPU management
• Asynchronous I/O to overlap with computation
• Interrupt
• Between instructions
• Within an instruction
• Enable and disable

CPU
Memory
Interrupt
11
Using Interrupts For Scheduling

• Timer interrupt
• Generated by hardware
• Assume changing requires privilege
• Delivered to the OS
• Main idea
• Before moving process to running, set timer
• If process yields/blocks, clear timer
• Timer expires? Go to scheduler

12
Scheduling Considerations

• Timer granularity
• Finer timers more responsive
• Coarse timers more efficient
• Accounting
• Cheap
• Accurate
• Fair consider I/O versus CPU applications

13
Preemptive Scheduling
Terminate (call scheduler)
Running
Scheduler dispatch
Block for resource (call scheduler)
Yield, Timer Interrupt (call scheduler)
Create
Ready
Blocked
I/O completion interrupt (move to ready queue)
14
The Simplistic Acquire/Release
Acquire() disable interrupts
Release() enable interrupts

• Kernel cannot let users disable interrupts
• Critical sections can be arbitrarily long
• Used on uniprocessors, but wont work on
  multiprocessors

15
Disabling Interrupts

• Done right, serializes activity
• People think sequentially easier to reason
• Guarantees code executes without interruption
• Delays handling of external events
• Used throughout the kernel

16
Using Disabling Interrupts
Acquire(lock) disable interrupts while
(lock ! FREE) enable interrupts
disable interrupts lock BUSY enable
interrupts
Release(lock) disable interrupts lock
FREE enable interrupts

• Why do we need to disable interrupts at all?
• Why do we need to enable interrupts inside the
  loop in Acquire?

17
Using Disabling Interrupts
Acquire(lock) disable interrupts while
(lock BUSY) enqueue me for lock
block else lock BUSY enable
interrupts
Release(lock) disable interrupts if
(anyone in queue) dequeue a thread
make it ready lock FREE enable
interrupts

• When does Acquire re-enable interrupts in going
  to sleep?
• Before enqueue?
• After enqueue but before block?

18
Hardware Support for Mutex

• Mutex mutual exclusion
• Early software-only approaches limited
• Hardware support became common
• Various approaches
• Disabling interrupts
• Atomic memory load and store
• Atomic read-modify-write
• L. Lamport, A Fast Mutual Exclusion Algorithm,
  ACM Trans. on Computer Systems, 5(1)1-11, Feb
  1987. use Google to find

19
The Big Picture
Concurrent Applications
High-Level Atomic API
Locks Semaphores Monitors Send/Receive
Low-Level Atomic Ops
Load/Store Interrupt disable TestSet
Interrupt (timer or I/O completion), Scheduling,
Multiprocessor
20
Atomic Read-Modify-Write Instructions

• TestSet Read value and write 1 back to memory
• Exchange (xchg, x86 architecture)
• Swap register and memory
• Compare and Exchange (cmpxchg, 486)
• If Dest (al,ax,eax), Dest SRC
• else (al,ax,eax) Dest
• LOCK prefix in x86
• Load link and conditional store (MIPS, Alpha)
• Read value in one instruction, do some operations
• When store, check if value has been modified. If
  not, ok otherwise, jump back to start

21
A Simple Solution with TestSet
Acquire(lock) while (!TAS(lock))
Release(lock) lock 0

• Waste CPU time
• Low priority threads may never get a chance to run

22
TestSet, Minimal Busy Waiting
Release(lock) while (!TAS(lock.guard))
if (anyone in queue) dequeue a thread
make it ready else lock.value 0
lock.guard 0
Acquire(lock) while (!TAS(lock.guard))
if (lock.value) enqueue the thread
block and lock.guard 0 else
lock.value 1 lock.guard 0

• Why does this work?