DECAP SIMULATIONS

1
XARXES DALIMENTACIÓ DELS CIRCUITS INTEGRATS
ANÀLISI I EXPERIMENTS (resum de temes inclosos en
la proposta de pla de formació)
Josep Rius Vázquez
Dept. dEnginyeria Electrònica, ETSEIB
2
On-chip decap modeling
frequency content of PSN
gate switching time ps
PSN
On-chip decoupling capacitors is an effective
practice to reduce PSN but
10

• how many ?
• where ?
• what size ?
• what about leakage ?

channel length nm
45 70 100 130 .
We are working in a decap model and a methodology
to analyze its response including gate leakage
answers depend on their behavior a model is
needed
3
AC response including leakage
1.1
Normalized voltage along the channel
1
VM ejwt
r, c
g
0.9
dL
v(x,t)
d
dL
0
L/2
x
0.8
0
L/2
-l
but at high w noise penetrate partially in the
decap. The skin depth dL is a measure of the
effective decap length at high w
Amplitude A(x) changes along the channel It
depends on r, c and g as well as w
At low w the decap behavior is as a lumped RC
circuit and noise is properly filtered
4
On-chip decap placement
VDD
GND
C1
It is important where to put the decaps in a
standard-cell block ?
C2
C3
5
The answer is yes
One standard-cell row model
6
Multiple rows model
VDD
VDD
GND
GND
Row 1
Row 2
Row 3
Row 4
Row 5
GND
GND
VDD
VDD
7
PDN resonances analysis and reduction
L
L
LR
L
L
Power Distribution Network can be described as a
complex LRC mesh with many oscillating modes
excited by distributed current sources.
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Lowest oscillating mode
F0
Resonant frequencies at an internal node
Z
F
48GHz
Below the frequencies of internal nodes, R, L, C
and i(t) can be considered lumped elements
9
Resonance in the PDN
F0
F
10
PDN resonance analysis and reduction

• Monitors to detect when the circuit activity
  produces resonance
• Passive and active counter measures.