SelfTimed Approach for Noise Reduction in NoC

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Self-Timed Approach for Noise Reduction in NoC

• Pasi Liljeberg, Johanna Tuominen, Sampo Tuuna,
  Juha Plosila, and Jouni Isoaho

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Outline

• On-Chip Noise Sources
• Self-Timed Techniques for Noise Reduction
• Case Study 1 Pipelined Bus
• Case Study 2 Viterbi Decoder
• Conclusion

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On-Chip Noise Sources

• As technology scales to deep submicron regime, it
  will be more difficult to manage different types
  of noise such as power supply noise, crosstalk,
  and leakage noise, because of the continuous
  scaling of supply and threshold voltages.

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On-Chip Noise Sources Power Supply Noise

• Power supply noise in digital ULSI chip mainly
  originates from simultaneous clock-induced
  switching of CMOS circuits which causes high peak
  current draws from the power source.
• The total power supply noise is the sum of IR
  voltage drop and the switching noise L?I ?V
  IR L?I / ?t
• The maximum ?I occurs when the maximum current
  change takes place. On the contrary the maximum
  IR drop occurs when the current is its peak.

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On-Chip Noise Sources-Power Supply Noise

• Decoupling capacitors are used to provide a
  stable power supply overall the chip. The area
  needed for these capacitors increases with the
  size and complexity of the chip.
• The transient shift of the power lines due to the
  switching noise introduces signal undershoots or
  overshoots to the active part of the circuit
• It presents also a potential problems for the
  quiet non-switching circuits where the noise
  often leads to signal ringing, longer settling
  times or it might even trigger false switching.

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On-Chip Noise Sources- Electromagnetic
Interference

• Electromagnetic interference (EMI) is defined as
  any unwanted conducted or radiated signals that
  degrade the operation of the electronic system.
• Technology scaling increases the sources of EMI
  due to the higher clock frequencies, dynamic
  power consumption and increased complexity.
• The simultaneous switching activity of
  transistors induces noise into a power supply
  network and can be conducted off-chip from power
  supply pins.
• The control of EMI is a complex problem which
  includes many aspects of design (on-chip and
  off-chip).

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On-Chip Noise Sources -Crosstalk

• Capacitive coupling is currently dominant, but
  inductive coupling becomes more and more
  significant as signal frequencies and on-chip
  wire lengths increase.
• Signal may temporarily assume an erroneous logic
  value gt may lead to a logical failure.
• Increases delay, if wire and another wire coupled
  to it are switching opposite direction.

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Crosstalk Influence of Design Parameters
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Crosstalk Influence of Design Parameters
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Crosstalk Influence of Switching Patterns
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Crosstalk Influence of Switching Patterns
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Properties of the Asynchronous Systems

• Asynchronous circuit is a self-timed device,
  whose operation is not paced with a global clock
  signal.
• Therefore to sequence the events of the system,
  the operation relies on controlling the order of
  transitions on control wires.
• The clock related problems of distributing the
  clock signal and concequences of the clock
  dictated operation can be avoided.
• Low-noise coefficients.

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Properties of the Asynchronous Systems

• Potential for the lower power consumption due to
  the natural support for the idle mode.
• Composability, because the self-timed circuits
  contains the timing and data requirements
  explicitly in their interfaces. Hence the term
  self-timed, they keep the time for themselves.

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Properties of the Asynchronous Systems

• Self-Timed circuit is 20 100 larger than its
  synchronous equivalen due to tis handshake logic.
  However the lack of clock circuitry saves area.
• Lack of commercial CAD-tools.
• Asynchronous system is more sensitive on glitches
  since there are no discrete time intervals.
  Therefore any glitch may cause the system to fail.

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Signaling Protocols
Self-timed signaling (a) 4-phase protocol (b)
2-phase protocol
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Four-Phase Dual-Rail Encoding
A delay-insensitive channel using 4-phase
dual-rail protocol
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1-of-4 Data Encoding

• A two-bit symbol is transmitted using four wires.
  For instance a two bit code, ('00', '01', '10',
  '11'), is transmitted by changing the signal
  level on just one of the four wires.
• 1-of-N encoding methods are delay insensitive.

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De-Synchronization

• The purpose is to decrease the number of
  simultaneous switching events so that the current
  peaks will be lower gt power supply noise and EMI
  is decreased.
• De-Synchronization does not require to re-design
  the entire system (e.g. Case Study 2).
• It is necessary only to add a self-timed control,
  re-route existing clock lines, and in some cases
  add register levels.

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Time-Interleaving

• Data is divided into bit groups which are
  transmitted at a slightly different times with
  respect to each other gt the power hungry bus
  drivers do not switch at the same moment of time.
• The current peak draw is reduced and therefore
  the power supply noise.
• For example a 32-bit message is divided into four
  groups, the first group contains the bits
  0,4,8,12,16,20,24,28.
• Neighboring bus drivers do not switch exactly at
  the same moment gt reduces crosstalk.

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Case Study 1 Pipelined Bus
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Implementation

• The pipelined bus was implemented by using a 0.13
  µm technology with 1.2 V supply voltage.
• The transmitted messages are 32-bit in all cases
  with 150 ps rise and fall times.
• The wires are placed 0.6 µm apart from each other
  and they have length of 2 mm, width of 0.6 µm and
  thickness of 0.32 µm.
• 2-phase data encoding techniques for the bus
  segment time-interleaving, dual-rail, 1-of-4
  encoding.

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Noise Characteristics of the Bus Segment

• The bus segment was analyzed using bundled data
  convention with two-phase signaling.
• All wires have possibility to switch
  synchronously gt reference point to noise
  analysis.
• The worst-case voltage coupling occurs when all
  the wires, except one in the middle, switch
  simultaneously. The maximum crosstalk voltage
  that is coupled to that wire is 144 mV or 12 of
  the supply voltage. The I(peak) 46 mA.

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Noise Characteristics of the Bus Segment
Crosstalk voltage of a synchronous bus segment
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Results
Crosstal and peak current in a function of
time-interleaving
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Results cont'd

• The amount of noise decreases when the time
  between bit groups increases.
• When the bus transactions are divided into
  four-bit groups with 70 ps time-interleaving, the
  peak current is decreased 43 and the crosstalk
  is reduced 37 .

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Results cont'd
Current profiles of a bus segment (a)
synchronous, (b) 1-of-4 encoding.
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Results cont'd

• The 1-of-4 encoding is attractive to low-power
  design point of view since the average current is
  decreased 53 compared to synchronous bus.
• Adjacent wires cannot switch in opposite
  direction. Crosstalk should not be as detrimental
  as it is for single-rail implementation.

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Case Study 2 Viterbi Decoder
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Self-Timed ACS-Unit
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The Structure of the self-timed PMU
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Interprocessor Communication

• Asynchronous Interconnects
• 4-Bit Time-Interleaved Interconnects
• Four-Phase Dual-Rail

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Area
Relative Areas in the 0.35 µm technology
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Area
Relative areas in the 0.18 µm technology
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Current Profiles
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Current Profiles
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Current Profiles
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Summary
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Conclusion

• The study considered in this chapter revealed the
  possibility to decrease the crosstalk and the
  power supply noise by utilizing self-timed design
  approach.