PowerAware Adaptive Issue Queue and Register File

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Power-Aware Adaptive Issue Queue and Register
File

• Jaume Abella1, Antonio González1,2

1 Computer Architecture Dept. UPC-Barcelona
2 Intel Barcelona Research Center Intel Labs
UPC, Barcelona
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Motivation (I)

• Power keeps on growing

S.H.Gunther, F.Binns, D.M.Carmean, J.C.Hall,
Managing the Impact of Increasing Power
Consumption, in Intel Technology Journal, 1st
quarter 2001
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Motivation (II)

• Higher power means higher temperature
• The cooling system becomes more expensive

S.H.Gunther, F.Binns, D.M.Carmean, J.C.Hall,
Managing the Impact of Increasing Power
Consumption, in Intel Technology Journal, 1st
quarter 2001
4
Motivation (III)

• Saving power in hotspots is crucial
• Issue logic
• Speculative data storage

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Objectives

• Saving energy in issue queue and register files
• Turning off empty banks
• Delaying the dispatch of some instructions, which
  increases the number of empty banks

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Contents

• Motivation
• Hardware model
• Issue queue
• Reorder buffer
• Register file
• Stalling instruction dispatch
• Results
• Conclusions

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Considerations

• Multiple-banked issue queue and register files
• Banks can be turned on/off independently

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Issue Queue (I)
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Issue Queue (II)

• Each bank has its own enable signal
• This signal gates
• Tagline for waking-up
• Vdd of CAM and RAM cells

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Reorder Buffer

• Its size determines the number of instructions
  in-flight
• Small energy consumption
• Does not store instructions results

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Register File

• A bank is turned on
• When one of its registers is allocated to an
  instruction
• A bank is turned off
• When all of its registers are free

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Contents

• Motivation
• Hardware model
• Issue queue
• Reorder buffer
• Register file
• Stalling instruction dispatch
• Results
• Conclusions

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Stalling Dispatch (I)

• Objective
• Reducing dynamically the size of the reorder
  buffer and the issue queue.
• Turning off empty banks is easy
• Some instructions spend some cycles in the issue
  queue before being issued
• Its dispatch may be delayed

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Stalling Dispatch (II)

• Reorder buffer limits the number of in-flight
  instructions
• If instructions wait too long in the issue queue,
  reduce reorder buffer size
• If reorder buffer is very small, it is better not
  to be very aggressive

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Stalling Dispatch (III)

• Fit issue queue size to the actual requirements
• If dispatch is stalled frequently (issue queue is
  full), increase its size
• If dispatch stalls are rare, decrease its size

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Resizing the Reorder Buffer (I)

• Implementation monitoring the following
  relationship
• FRACTION IQ_occupancy / ROB_occupancy
• If FRACTION is high
• Instructions are considered no power efficient
• If FRACTION is low
• Instructions are considered power efficient

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Resizing the Reorder Buffer (II)

• Mechanism

1
Threshold_high
IQ occupancy
FRACTION
ROB occupancy
Threshold_low
0
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Resizing the Reorder Buffer (III)

• ROB size is large be aggressive

1
Threshold_high
Decrease thresholds
Threshold_low
0
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Resizing the Reorder Buffer (IV)

• ROB size is small be conservative

1
Threshold_high
Increase thresholds
Threshold_low
0
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Contents

• Motivation
• Hardware model
• Issue queue
• Reorder buffer
• Register file
• Stalling instruction dispatch
• Results
• Conclusions

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Evaluation Framework

• Processor (8-way superscalar)
• Reorder buffer size 128 instructions
• Issue queue size 80 instructions
• Registers 112 integer 112 FP physical
  registers
• Benchmarks
• SpecINT2000 and SpecFP2000
• Simulator
• Wattch and CACTI

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Baseline

• Comparison with mechanism by Folegnani and
  González (ISCA 2001)
• Based on IPC contribution of the youngest part of
  the issue queue
• If IPC of the youngest part is below a threshold,
  decrease issue queue size
• Every certain interval, increase issue queue size

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IPC
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Issue Queue Energy Savings
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Register File Energy Savings
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Contents

• Motivation
• Hardware model
• Issue queue
• Reorder buffer
• Register file
• Stalling instruction dispatch
• Results
• Conclusions

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Conclusions

• Delaying the dispatch and a simple
  multiple-banked structure is proposed
• High power savings in issue queue and register
  file
• IPC is not the only relevant parameter for
  structure resizing
• Queue occupancy is also very relevant
• Saving power in the hotspots is crucial for
  temperature
• Our approach is also expected to reduce the
  temperature

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Q A