BCM

1

• BCM BPM
• PCI Data Acquisition
• Timing Decoder
• Joe Mead

2
Overview

• Requirements
• Implementation
• Status

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Requirements

• Data Acquisition
• Read ADCs, buffer in local SSRAM
• Read data out via PCI bus
• Event Decoder
• Decode Triggers from Event Link (Cycle Start,
  Diag-Fast, etc.)
• Decode Timestamp from RTDL
• Provide programmable delay for Cycle Start
  trigger
• Front End Control
• Programmable Gain (Both BCM and BPM)
• Interface to Calibrator Board (BCM)
• Interface to RF Synthesizer (BPM)

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Block Diagram
5
BCM layout
Calibrator Interface
BCM Front End Interface
256k 64 SSRAM
Event Link Input
RTDL Input
Trigger Input
Rsvd. Output
Altera JTAG port
EPC16
3.3v 5v translators
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BPM layout
Calibrator Interface (not used on BPM)
BPM Front End
256k 64 SSRAM
Event Link Input
RTDL Input
Trigger Input
Rsvd. Output
Altera JTAG port
EPC16
3.3v 5v translators
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Status Data Acquisition

• Successfully acquiring ADC data at sampling rates
  up to 84MS/s.

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Status Data Acquisition

• Currently not utilizing full PCI bandwidth
• Reading data through PCI bus as in non DMA
  fashion
• Currently takes approx. 75ms to read a 70k data
  set
• 42MS/s for 1.6mS 70k points
• Need to improve PCI bandwidth
• Implement DMA
• Estimated Time to Complete 3-4 weeks

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Status Event Link RTDL Decoder

• Successfully decoding both Event Link and RTDL
  events, using code developed by Craig Swanson at
  ORNL

Bi-Phase Event link input
Decoded clock
Decoded Start Bit
Decoded Data Output
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Status Event Link RTDL Decoder

• Asynchronous vs. Synchronous Sampling
• The current decoded clock of event link has a
  pk-pk jitter of 7.6ns, which would limit the
  theoretical SNR for an ADC, as limited by
  aperture uncertainty to about 20dB.
• Need to have a better implementation of decoding
  the event link clock
• Or, use an on-board oscillator to drive the ADCs
  asynchronous to the beam

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Status Front End Control

• BCM
• Programmable Gain control Complete
• Need to integrate with Calibrator board
• Estimated time to complete 1-2 weeks
• BPM
• Programmable Gain Control Complete
• Need to integrate with RF section
• Estimated time to complete 1-2 weeks

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Status Parts

• Total Component Cost / bd 450
• Have in stock major components
• Altera FPGA (225 ea)
• Altera Configuration EEPROM (44 ea)
• SSRAM (15 ea, 2 per board)
• Still need to order cheaper ICs, connectors,
  etc. (150 per board)