Dynamic Random Access Memory: 3transistor Cells

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Dynamic Random Access Memory 3-transistor Cells

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• Jacien Squires

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Reason for Choosing Design

• Dram is a topic of interest.
• Debate over performance of different types.
• Pc133 SDRAM.
• DDR SDRAM.
• RDRAM.
• Wanted to know how these memories were
  constructed.

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Final/ Intended Application

• Construct small, 4-bit memory column using DRAM
  cell.
• Columns are used to make blocks of memory.
• Similar to what would be found in PC memory.

4
Design Constraints

• DRAM cell had to use 3 transistors.
• Newer designs use 1 transistor.
• Cell uses capacitor.
• Could have used internal capacitance of
  transistor.
• Was unsure of how to achieve this.

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What DRAM Does

• DRAM is a read-write memory that fulfills the
  large data and program storage requirements of
  todays computers.
• Typical size is 64 megabytes.

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Advantages of DRAM

• Higher memory density.
• Low power dissipation.
• Low transistor count (1 3 transistors per
  cell).

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Disadvantages of DRAM

• Expense of added circuit complexity .
• Longer read and write times.
• Delays due to refresh requirements.

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How DRAM Works
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How DRAM Works Cont.

• Write enable set high.
• Data written by write pin.
• Capacitor stores data signal.
• Periodic refresh required to keep signal stored.

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How DRAM Works Cont.

• Setting read enable allows data to be read.
• Data is outputted through read pin.

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Simulations

• Added forces to write, write enable, and read
  enable pins.

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Simulations Cont.
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Layout
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Post-layout Simulations
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Unexpected Glitches

• Slight problem in wiring the circuit.
• Did not have transistors grounded properly.
• Fixing this eliminated simulation errors.
• Had to manually design cell layout.
• Auto floor plan would not work.
• Had to add ports to cell layout for simulation to
  work.

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Future Work

• Design 4-bit memory Column.

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Proposed Schedule

• Week of January 21begin research of project.
• Week of January 28begin designing project.
• Week of February 14complete design, begin
  testing.
• Week of February 18complete testing, finish
  report.
• Week of march 4...Give project presentation.

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Actual Schedule

• Week of January 21began research of project/
  started report.
• Week of January 28began designing project.
• Week of February 25completed design/ began
  testing.
• Week of march 4completed testing, gave project
  presentation, finished report.

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Summary

• Completed schematic design and simulation.
• Schematic simulation successful.
• Completed cell design and simulation.
• Cell simulation incomplete.
• Achieved goal of learning how DRAM is constructed.