Introduction to VHDL

1
Introduction to VHDL

• CpE311
• Winter 2002

2
Introduction to VHDL Outline

• Part 1
• Generic Introduction to VHDL
• Examples
• vcom/vsim
• Part 2
• Using VHDL for hardware Synthesis
• Leonardo

3
Intro to VHDL

• VHDL
• VHSIC Hardware Description Language
• Developed by TI, IBM, Intermetrics in 1983
• IEEE Std 1076-1987 and 1993
• VHSIC
• Pronounced Vi-Sik
• Very High Speed Integrated Circuits
• DOD program in 1981.

4
Intro to VHDL Background

• VHDL is a Hardware Description Language, not a
  programming language!
• Our Emphasis is on description for synthesis not
  hardware modeling
• VHDL is Ada based (which is Pascal based)
• Most Major EDA tool vendors now support VHDL
• Main competitor language is Verilog (C-based)
• Applies to all digital hardware
• Systems, Boards, ASICs
• PLDs, CPLDs, FPGAs, StdCell, GA etc

5
VHDL References

• Mentor Graphics - hdl_syn.pdf (on CpE 311
  website)
• Ashenden - www.ashenden.com.au/
• Accolade Tutorial - www.acc-eda.com/vhdlref/index.
  html
• Perry - VHDL, McGraw Hill.
• J. R. Armstrong - Chip level modeling with VHDL,
  Prentice Hall
• Yalamanchili, VHDL starters guide, PrenHall
• Bhasker - A VHDL Primer - Revised Edition,
  Prentice Hall, 1995.

6
VHDL Capabilities

• Exchange medium for tools and vendors
• Flexible Design Methodologies - top/down or
  bottom/up or mixed.
• Technology Independent
• Non-proprietary. IEEE Standard
• Behavioral, Dataflow, Structural Descriptions
• VHDL Test benches (self contained)
• Simulation or Synthesis
• Many others too numerous to mention

7
BASIC Elements of VHDL

• Identifiers - comments, names, labels
• Data Objects - constants, variables, signals
• Data Types - eg. integer, bit, bit_vector,
  std_ulogic
• Operators
• Logical (AND, OR, NAND, NOR, XOR, NOT)
• Assignment var () signal lt ()
• Arithmetic ,-,,,/,mod,rem,abs,
• Relational ,/,lt,lt,gt,gt
• VHDL Design - Entity, Architecture, Package,
  Library
• Everything is a Process

8
VHDL Entity

• Entity Black Box
• Defines external interface
• Ports are like pins
• Mode in, out, inout
• Type eg. bit, bit_vector
• Name eg. A, B, Y
• Example
• entity F is
• port(A,B in bit Y out bit)
• end F

9
Example Entity (mux2)

• ENTITY mux2_1 IS
• PORT (in0, in1, sel IN BIT
• yout OUT BIT)
• END mux2_1

10
VHDL Architecture

• One or more architectures per entity
• Dataflow - similar to logic equations
• Behavioral
• Highest Level - similar to a program
• Structural
• like a netlist - shows how components are
  connected
• Can mix and match architecture styles

11
Mux2_1 Architecture

• Dataflow
• ARCHITECTURE a1 OF mux2_1 IS
• BEGIN
• yout lt ((in0 AND NOT(sel)) OR (in1 AND sel))
• END a1

12
Mux2_1 Architecture

• Structural
• ARCHITECTURE a2 OF mux2_1 IS
• SIGNAL sel_not, in0_and, in1_and BIT
• COMPONENT OR_GATE PORT(x,y IN BIT z OUT BIT)
• COMPONENT AND_GATE PORT (x,y IN BIT z OUT
  BIT)
• COMPONENT INV_GATE PORT (x IN BIT z OUT BIT)
• BEGIN
• U1 AND_GATE PORT MAP (in0, sel_not, in0_and)
• U2 AND_GATE PORT MAP (in1, sel, in1_and)
• U3 INV_GATE PORT MAP (sel, sel_not)
• U4 OR_GATE PORT MAP (in0_and, in1_and, yout)
• END a2

13
Control Statements

• PROCESS Statements
• Signal assignment x lt y
• Process block
• p1PROCESS (clk)
• BEGIN ... --sequential statements
• END PROCESS
• All processes execute concurrently (in parallel)
• Sequential Statements
• Normal program statements if/then/else case
• MUST occur within a process block

14
Mux2_1 Architecture

• Behavioral
• ARCHITECTURE a3 OF mux2_1 IS
• P1 Process (sel, in0, in1)
• Begin
• IF (sel 0) THEN
• yout lt in0
• ELSE
• yout lt in1
• END IF
• END P1
• END a3

15
More Control Statements

• IF / THEN / ELSE / END IF
• CASE / WHEN / END CASE
• LOOP - like For/Next or DO loops
• What hardware does that imply?
• All must occur within a PROCESS block
• Why? (think about it)
• Can use everything for Test Benches but be
  careful when describing hardware to be
  synthesized!

16
CASE ... WHEN ...

• Useful for implementing State Machines
• Example
• TYPE states IS (s1,s2,s3)
• SIGNAL state states s3 in bit
• sm PROCESS (clk)
• CASE state IS
• WHEN s1 gt
• IF (in 0) THEN state lt s2 ELSE
• state lt s1
• WHEN s2 gt
• IF (in 1) THEN state lt s3 ELSE
• state lt s1
• WHEN s3 gt
• state lt s1
• END CASE

17
VCOM

• vcom - Mentors VHDL compiler
• Uses Model Technologys VHDL kernel
• Complete implementation of VHDL
• Use with Design Architect or Command Line
• vcom design.vhd

18
VSIM

• vsim is Mentors VHDL Simulator
• Considerably different from Quicksim
• Model Technologys VHDL simulator
• Many nice features for debugging VHDL
• Refer to online documentation for tutorial
• Invoke from command line vsim
• Or specify entity/arch pair vsim e1 a1
• Or specify a configuration vsim c1

19
Using VCOM and VSIM

• 1. Create a work directory in your current dir
• vlib work
• 2. Compile source file
• vcom circuit.vhd
• 3. Simulate circuit description
• vsim
• 4. Iterate 2 and 3 as required.

20
Summary - Part I

• VHDL is NOT a programming language, even though
  it can be used as one
• Think in terms of hardware when writing VHDL
• ex1. what does IF (xlty) then z lt w really mean?
• ex2 IF (in0) THEN zltx0y0 ELSE zltx1y1
• vs IF (in0) THEN txltx0 tylty0
• ELSE txltx1 tylty1 END IF
• z lt tx ty
• Which is better? Why?

21
For next time

• Assignment Use vcom and vsim to compile and
  simulate simple VHDL models
• A half gate (see MJSS 8.3)
• A combinational device like a 7-seg decoder
• 2. A simple state machine like a JK flip flop
• Examine Synthesis Related Issues
• Using Exemplars Leonardo with Actel target
  technology.

22
VHDL - Part II

• Using VHDL for hardware Synthesis
• See /usr/local/galileo/doc/hdl_syn.pdf for
  details
• Leonardo (aka LeonardoSpectrum)
• References
• leo_user.pdf Users guide
• leo_cmds.pdf Command reference
• leo_tech.pdf Actel specifics
• All are in /usr/local/galileo/doc

23
Level Sensitive Latch

• signal input_foo, output_foo, ena bit
• ...
• dlat process (ena, input_foo)
• begin
• if (ena 1) then
• output_foo lt input_foo
• end if
• end process

24
Edge triggered flip flops

• signal input_foo, output_foo, clk bit
• ....
• dff process (clk)
• begin
• if (clkevent and clk1) then
• output_foo lt input_foo
• end if
• end process

clk
25
Synchronous Sets and Resets

• signal input_foo, output_foo, clk, reset bit
• ...
• dffr process (clk)
• begin
• if (clkevent and clk 1) then
• if reset 1 then
• output_foo lt 0
• else
• output_foo lt input_foo
• end if
• end if
• end process

26
Flip flop with wait until clause

• signal input_foo, output_foo, clk, reset bit
• ...
• dffr process -- no sensitivity list!
• begin
• wait until clk1
• if reset 1 then
• output_foo lt 0
• else
• output_foo lt input_foo
• end if
• end process

27
Asynchronous Sets and Resets

• signal input_foo, output_foo, clk, reset bit
• process (clk,reset)
• begin
• if (reset 1) then
• -- put other combinational logic here
• output_foo lt 0
• elsif (clkevent and clk 1) then
• -- put other sequential logic here
• output_foo lt input_foo
• end if
• end process

28
Clock enable

• May not be available in all technologies

signal input_foo, output_foo, enable, clk
bit dffce process (clk) begin if (clkevent
and clk1) then if (enable1) then
output_foo lt input_foo end if end if
end process
29
Variables

• signal input_foo, output_foo, clk bit
• process (clk) --a clocked process
• variable a, b bit
• begin
• if (clkevent and clk1) then
• output_foo lt b --use b before assigned
• b a --use a before assigned
• a input_foo
• end if
• end process

this is a 3-bit shift register!
30
Using I/O buffers

• --declare ieee standard logic package
• library ieee
• use ieee.std_logic_1164.all
• entity example is
• port ( inp, clk in std_logic --inbuf
• outp out std_logic --outbuf
• inoutp inout std_logic --bibuf
• )
• end entity example
• --use chip mode in leonardo
• --top level signals get i/o buffers.
• --outplt 1 if ena1 else Z for tribuf

31
Tri state buses

• entity three-state is
• port ( in1, in2 in std_logic
• ena_1, ena_2 in std_logic
• outsig out std_logic)
• end three-state
• architecture a1 of three-state is
• begin
• outsig lt in1 when ena_1 1 else Z
• outsig lt in2 when ena_2 1 else Z
• end a1
• Normally cant have two drivers like this
• Internal tri-states allowed in some technologies

32
Finite State Machine with Data Path(FSMD)
Inputs
Controller (FSM)
Data Path(ALU, Registers, Buses, etc)
Control Signals
Status Signals
Outputs
33
Finite State Machine
Combin- ational Logic
Reg
next state
current state
inputs
outputs
clock
34
Two process state machines(Process 1, current
state register)

• entity dramctrl is
• port ( clk, cs, refresh, reset in bit
• ras, cas, ready out bit )
• end dramctrl
• architecture a1 of dramctrl is
• -- Define the possible states of the state
  machine
• type statetype is (s0, s1, s2, s3, s4)
• signal currentstate, next_state statetype
• begin
• registers process (clk, reset)
• begin
• -- process to update the current state
• if (reset1) then
• currentstate lt s0
• elsif clkevent and clk 1 then
• currentstate lt nextstate
• end if
• end process

35
Next State Process(Combinational Logic)

• transitions process (currentstate, refresh, cs)
• begin --next state calculation
• raslt 0 caslt0 readylt0
  nextstatelts0--default
• case currentstate is -- some when clauses
  removed.
• when s0 gt
• ras lt 1 cas lt 1 ready lt 1
• if (refresh 1) then nextstate lt s3
• elsif (cs 1) then nextstate lt s1
• else
• next_state lt s0
• end if
• when s1 gt
• ras lt 0 cas lt 1 ready lt 0
• next_state lt s2
• end case
• end process
• end a1

36
State machines summary

• Use two process template
• Use a case statement, not nested IFs
• IFs result in a priority encoder which uses more
  logic
• Use a symbolic state assignment
• Let the synthesis tool generate the state
  assignment
• Use a default value for outputs and nextstate at
  the start of the process to avoid latches.

37
Arithmetic Operators

• Operators , -, , / , , /, lt, gt, lt, and gt
  only defined for integers in standard vhdl.
• Use a package like std_logic_arith for other
  types
• Default size is 32 bits
• Default type is twos complement
• A Combinational multiply is generated by
• Can only divide by powers of two
• See Leonardo doc for details.
• Arithmetic is highly tool dependent!

38
Addition operator

• Use ranged integer variables or signals
• Heres an 8 bit unsigned adder
• Heres a 4 bit signed adder
• Caveat youll need to convert to bits!

variable a, b, c integer range 0 to 255 c
a b
variable a, b, c integer range -8 to 7 c a
b
39
Other considerations

• Module generation
• Leonardo can infer technology dependent hard
  macros like adders
• Resource sharing
• These two are equivalent

if ( ab c ) then s1 elsif ( ab d) then
s2 end if
tmp ab if ( tmp c ) then s1 elsif ( tmp
d) then s2 end if
40
Down versus Up counters

• Here are two mod n counters. Which is best?

process begin wait until clk1 if (count n)
then count 0 else count count 1 end
if end process
process begin wait until clk1 if (count 0)
then count n else count count - 1 end
if end process
Note variable count integer range 0 to 255
41
Summary

• Think hardware when writing VHDL for synthesis
• Dont try to get fancy. Keep it simple.
• See hdl_syn for more examples and tips
• Use actgen to generate other examples
• See CpE311 web page for online tutorials
• www.ece.umr.edu/hjp/ee311

42
Synthesis design flow(Example)

• Generate VHDL source
• eg. Use actgen to generate a four bit adder
• Compile with vcom
• Functional Simulation with vsim
• Synthesize with leonardo
• Place and route with designer
• Timing simulation with vsim

43
Generate VHDL source

• actgen
• select a module
• fill in form
• FilegtGenerate

44
Generate VHDL source

• actgen
• select a module
• fill in form
• FilegtGenerate
• select vhdl format
• enter filename
• See add4_behave.vhd example

45
Add4 behave.vhd

• entity add4 is
• port(DataA, DataB in UNSIGNED(3 downto 0)
• Sum out UNSIGNED(3 downto 0))
• end add4
• architecture behavioral of add4 is
• begin
• process (DataA, DataB)
• begin
• Sum lt DataA DataB
• end process
• end behavioral

46
Compile with vcom

• vlib work (or qhlib)
• only need to do this once
• vcom add4_behave.vhd
• puts compiled code into work library

47
Functional simulation

• vsim add4 behavioral
• add wave
• force dataa 0000
• force dataa 0101 100
• force datab 0011 200
• run 300

48
Synthesize

• leonardo
• Select technology
• act1 A1010BPL44
• Open input file
• add4_behave.vhd
• run flow

49
Synthesis output

• RTL and Tech schematics
• Summary file
• area report
• timing report
• critical paths
• Edif file
• add4_behave.edf

50
Place and route

• designer
• generate fuse file
• if programming a part
• extract vhdl netlist
• extract SDF
• timing file

(DELAYFILE (SDFVERSION "2.1") (DESIGN
"add4_behave") (DATE "Wed Oct 06 204951
1999") (VENDOR "Actel")
51
Import netlist
EDIF file (edif add4 (edifVersion 2 0 0)
(edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timestamp 1999 10 07 01
48 00) (program "LeonardoSpectrum Level 3"
(version "v1999.1d")) (author "Exemplar Logic
Inc")))
52
Setup design
And select 1010BPL44 part with defaults
53
Timing simulation with vsim

• compile extracted netlist
• vcom add4_struct.vhd
• Simulate structural model with sdf file
• vsim -sdfmax add4_behave.sdf add4 struct