Neon Graphics Accelerator

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Neon Graphics Accelerator

• Anselmo Lastra

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History

• A proposed DEC product
• Never sold, as far as I know
• They were bought by COMPAQ
• Later HP
• Paper at 1998 Graphics Hardware
• Take into account that this was in the days of
  3dfx Voodoo
• Not too many sources of info on one-chip GPUs

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Rasterizer-Side Only

• Geometry processing on host
• A fast Alpha workstation
• Common on early PC products also

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Block Diagram
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Unified Memory

• They argue for single memory
• Common now, of course
• Can trade off one type for another
• Smaller FB More Texture
• Say that texturing can cause thrashing between
  texels and color/Z
• Is unified memory the best way to go?

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Fragment Generator

• Each cycle generates one of
• Single textured fragment
• 2x2 square of z-buffered fragments with color
  (64-bits data)
• RGB alpha
• Z
• Fog intensity
• 8 fragments with 32-bit solid color (or stipple
  pattern)
• 32 8-bit 2D fragments

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Texel Central

• More than just for textures
• Also frame buffer transfers go through here
• DMA to memory, Bit Blts
• Texture maps one fragment per clock

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Pixel Processors

• Eight of them
• One per memory controller
• Responsible for
• Z test
• Alpha
• Stencil
• Fog
• Blending
• Dithering

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Video Controller

• Always requests data from both bank A and B
• Memory controller chooses bank to maximize memory
  throughput
• Video controller can request data immediately

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Memory Controllers

• 8 separate memory controllers
• Each 32 bits wide
• 32 total 100MHz SDRAM chips
• SDRAMs can have up to 4 banks
• 23 address and control pins per controller
• Total of 440 pins for memory

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Memory Controller

• Frame buffer partitioned across the 8
• Five request queues each
• Reads from Texel Central
• Read and Write from Pixel Processors
• A and B bank reads from video controller
• Chooses from among queues to minimize memory
  cycle waste
• Any balancing between that and stalling units?
• Each controller has texture cache, 8 32-bit
  texels, fully associative
• Small

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Fragment Batches

• Batch of z comparisons and z/color writes
• Need to detect when two fragments belong to same
  pixel
• 8-way fully-associative overlap detector
• Detector terminates batch if incoming fragment
  overlaps
• Writes all data for terminated batch before
  reading new

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Interleaved Frame Buffer

• Checkerboard but rotated
• They suggest that 2x2 or 4x4 pixel batches would
  be better
• Would need more memory at controllers

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Fragment Generation

• Chunked or tiled
• Already discussed this

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Memory Usage (from slides)
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Performance Counters

• Two 64-bit counters

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Chip

• To show how much area/function
• Lot of space devoted to MC
• Includes caches and request queues

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Design Details

• They used C simulator
• Wrote a C to Verilog tool
• Developed some synthesis tools to help Synopsis

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Technical Report

• Much more detail in Tech Report
• Might be useful for people implementing
  particular parts of pipeline
• Texture addressing and filtering, for example