Bambang A' B' Sarif

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Logic Synthesis Using SIS

• Bambang A. B. Sarif
• COE-KFUPM

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Agenda

• Introduction
• Logic Synthesis Using SIS
• Combinational Logic Synthesis
• Sequential Logic Synthesis
• Technology Mapping
• Input File Format
• Example

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Introduction

• Early effort on Logic synthesis is dated back in
  the early 50s and 60s
• Quine and McCluskey algorithms
• Two level logic synthesis (1984)
• ESPRESSO
• Multi level logic synthesis
• Combinational Logic (1987) MIS
• Sequential Logic (1990) SIS

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Introduction ESPRESSO

• Running time of Quine McCluskey algorithm is
  O(3n/n)
• Finding minimum cover is an NP-complete problem
  
• ESPRESSO
• Trades speed with exact solution
• Using heuristic
• Procedures of ESPRESSO
• Expand expand prime implicants to its highest
  cover
• Irredundant Cover remove redundant implicants
• Reduce reduce prime implicants

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Introduction SIS

• It was developed by CAD research group of UC
  Berkeley (http//www-cad.eecs.berkeley.edu/)
• It is a software package consisting of tools for
  logic synthesis
• ESPRESSO, MIS, NOVA, JEDI, etc.
• Synthesis process is roughly divided into two
  phases
• Technology independent phase
• Technology dependent phase (technology mapping)

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Introduction SIS(2)

• SIS can be executed using batch files
• It is available in ccse network in /tools/sis/
• Documentations are available in /tools/sis/doc/
  and in http//www.ccse.kfupm.edu.sa/sarif/logic_s
  ynthesis.htm

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Logic Synthesis using SISSIS Environment (1)

• To invoke SIS, type SIS in your shell
• To exit from SIS environment, type quit
• To execute a unix command in SIS environment, use
  ! before the command
• Example sisgt!type adder.eqn
• SIS can be executed in batch mode (either command
  line or file script). Example
• sarifgtsis -t type1 T type2 -o outname -f
  scriptname lt inputname gt result.txt
• Will invoke SIS using type1 input file whose
  name is inputname, using script file scriptname,
  write the output in type2 format with filename
  outname and dump all result in result.txt file

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Logic Synthesis using SISSIS Environment (2)

• To print all SIS commands print_help
• SIS commands is categorized into several classes
• Input/output commands
• Network manipulation commands
• Network status command
• Etc

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Logic Synthesis using SISInput and Output
Commands

• Input commands read the circuits (network) or
  set some constraints
• Usually begin with read_. Example read_eqn,
  read_pla, read_blif
• Sets some parameters using set_ commands
  set_delay, set_state
• Output commands write the networks
• Usually begin with write_. Example write_pla,
  write_eqn, write_bdnet

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Logic Synthesis using SISNetwork Status Commands

• To print the required information. Usually begin
  with print_.
• Example print, print_stats, print_delay,
  print_kernel, print_gates, print_map_stats
• Other power_estimate, power_print

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Logic Synthesis using SISNetwork Manipulation
Commands

• This type of commands are used to manipulate
  our network to get the most optimize
  representations.
• There is no stick rule on which commands to use
  nor the order to invoke those commands
• Everybody are welcomed to experiments with
  their own approach to get the best results
• The commands can be divided roughly into commands
  for combinational and sequential logic circuits.

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Logic Synthesis using SIS Combinational Logic
Synthesis

• Combinational logic synthesis in SIS is targeting
  multi level logic form through these steps
• Decomposition
• Extraction
• Factoring
• Substitution
• Collapsing
• The input file can be in the form of pla, blif,
  eqn or slif command
• The commonly used commands are simplify,
  full_simplify, resub, eliminate, fx, gx, gcx,
  sweep

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Logic Synthesis using SIS Combinational Logic
Synthesis (2)

• There is a famous script used for combinational
  circuits targeting area minimization, i.e.,
  rugged.script. The script contains the following
  commands
• sweep eliminate
• simplify -m nocomp
• eliminate
• sweep eliminate
• simplify -m nocomp
• resub -a
• fx
• resub a sweep
• eliminate sweep
• full_simplify -m nocomp

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Logic Synthesis using SIS Combinational Logic
Synthesis (3)

• Script used for combinational circuits targeting
  delay minimization, i.e., delay.script contains
  the following
• sweep decomp -q
• tech_decomp -o 2
• resub -a d sweep
• reduce_depth -b -r
• red_removal
• eliminate -l 100 -1
• simplify -l
• full_simplify -l
• sweep decomp -q
• fx -l
• tech_decomp -o 2

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Logic Synthesis using SIS Sequential Logic
Synthesis

• Divided roughly into two parts the minimization
  of sequential parts and minimization of
  combinational parts of the circuits.
• The input file can be in the form of blif, slif,
  kiss or stg file.
• The minimization of sequential part consists of
• State minimization using STAMINA
• State assignment using NOVA or JEDI
• Retiming (retiming and resynthesis)

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Logic Synthesis using SIS Technology Mapping (1)

• Technology library is given in genlib format and
  should be read before technology mapping.
• The technology mapping is based on tree-covering
  algorithm decompose the functions into 2-input
  NAND gates and inverters, then covered by
  patterns that represents the possible choices of
  gate in the library.
• Effective for area minimization
• The mapping is performed by using map command.
• There is option for area (delay) optimization
  with delay (area) consideration

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Logic Synthesis using SIS Technology Mapping (2)

• Example of how different technology mapping for a
  4-bit ripple carry adder
• Command Area Delay
• map -m 0.5 AFW 45 gates, 64960.00 12.33
• map -n 1 AFGW 43 gates, 63104.00 11.89
• map -m 0 27 gates, 47328.00 16.45
• map -m 0.5 35 gates, 54752.00 14.00
• map -m 1 39 gates, 66352.00 14.97

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Logic Synthesis using SIS Input File Format (1)

• Equation file (eqn)
• The logic equations are of the form signal
  expression
• The following operators may be used to construct
  the expression
• ( ) grouping
• or or space AND
• or OR
• ! (prefix) or (postfix) NOT
• ! or XOR
• XNOR
• Hence, F a!b c!d and F a b' c d'
  represent the same equation

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Logic Synthesis using SIS Input File Format (2)

• The commands INORDER and OUTORDER can be used to
  specify the primary inputs and primary outputs
  for the network.
• For example
• INORDER a b c d
• OUTORDER p
• t c !b
• p !da !t!a

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Logic Synthesis using SIS Input File Format (3)

• PLA (truth table) format
• The following keywords are recognised, where d
  denotes a decimal number and s denotes a text
  string.
• .i d Specifies the number of input variables.
• .o d Specifies the number of output
  functions.
• .ilb s1 s2 . . . sn Gives the names of
  the input variables.
• .ob s1 s2 . . . sn Gives the names of the
  output functions.
• .p d Specifies the number of product terms.
  (optional)
• The product terms (one per line) are now
  specified -
• inputs outputs (See below)
• .e or .end Marks the end of the description.
• Comments are allowed within the input file,
  following a character.

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Logic Synthesis using SIS Input File Format (4)
(A,B,C,D) m(4,5,6,8,9,10,13) d(0,7,15)
-- inputs -- outputs -- input names -- output
name -- number of product terms -- A'BC'D' --
A'BC'D -- A'BCD' -- AB'C'D' -- AB'C'D --
AB'CD' -- ABC'D -- A'B'C'D' don't care -- A'BCD
don't care -- ABCD don't care -- end of list
.i 4 .o 1 .ilb a b c d .ob f .p 10 0100 1 0101
1 0110 1 1000 1 1001 1 1010 1 1101
1 0000 - 0111 - 1111 - .e
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Logic Synthesis using SIS Input File Format (5)

• KISS2 (state table) format
• In order to represent sequential designs, the
  previous truth-table format is extended to
  include present state and next state entries,
  so allowing state tables to be described.
• The following commands are used
• .s d Specifies the number of states.
  (optional)
• .r s Specifies the reset state. (optional)
• The entries in the state table are now given -
• inputs current_state next_state outputs
• where current_state and next_state are symbolic
  names representing the circuit states.

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Logic Synthesis using SIS Input File Format (6)

• Example
• .i 1
• .o 1
• 0 st0 st0 0
• 1 st0 st1 0
• 0 st1 st2 0
• 1 st1 st1 0
• 0 st2 st0 0
• 1 st2 st1 1
• .e

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Logic Synthesis using SIS Input File Format (7)

• BLIF Format
• Describe the hierarchical logic level of a given
  circuit in a textual form.
• A circuit is viewed as directed graph of
  combinational and sequential logic nodes.
• The format consists of the following information
• Model flattened hierarchical circuit (input,
  output, clock)
• Logic gates
• External dont cares
• Flip-flop and latches
• Library gates
• Model (subcircuit) references
• Subfile references
• FSM description (KISS format)
• Clock constraints
• Delay constraints

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Logic Synthesis using SIS Input File Format (7)

• Genlib Format
• It is used to specify the gates in SIS
• A cell is specified in the following format
• GATE ltcell-namegt ltcell-areagt ltcell-logic
  functiongt
• ltpin-infogt
• .
• ltpin-infogt
• A pin is specified in the following format
• PIN ltpin-namegt ltphasegt ltinput-loadgt ltmax-loadgt
  ltrise-block delaygt ltrise-fanout-delaygtltfall-block-
  delaygtltfall-fanout-delaygt

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Logic Synthesis using SIS Input File Format (8)

• A latch is specified in the following format
• LATCH ltcell-namegt ltcell-areagt ltcell-logic-functio
  ngt
• ltpin-infogt
• ltpin-infogt
• ltlatch-specgt
• ltclock-delay-infogt ltconstraints-infogt
• Latch-spec is defined as
• SEQ ltlatch-inputgt ltlatch-outputgt ltlatch-typegt

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Example Combinational Logic (1)

• FULL Adder
• PLA file (fa.pla)
• Full Adder
• .i 3.o 2.ilb a b cin.ob sum co.p 8000 0
  0001 1 0010 1 0011 0 1100 1 0101 0 1110 0
  1111 1 1.e

• Invoke SIS and read the pla file
• sis
• UC Berkeley, SIS 1.3
• sisgtread_pla fa.pla
• sisgtp
• sum a b cin a b' cin' a' b cin' a' b'
  cinco a b cin a b cin' a b' cin a' b
  cin
• sisgt simplify
• sisgt print
• co a b a ci b ci
• sum a b ci a b' ci' a' b ci' a' b' ci
• sis gt print_factor
• co ci (b a) a b
• sum ci (a' b' a b) ci' (a b' a' b)

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Example Combinational Logic (2)

• sisgt tech_decomp -o 4 -a 4
• sisgt print
• co 848 849 850
• sum 844 845 846 847
• 844 a b' ci'
• 845 a' b ci'
• 846 a' b' ci
• 847 a b ci
• 848 b ci
• 849 a ci
• 850 a b

• sisgt read_library msu.genlib
• sisgt map
• sisgt print
• co a b a ci b ci
• 1207 a'
• 1205 b'
• 1214 1205 1207 ci a b ci
• 844 1207' b' ci'
• 845 1205' a' ci'
• sum 1214 844 845

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Example Combinational Logic (3)

• sisgt print_map_stats
• Total Area 352.00
• Gate Count 12
• Buffer Count 0
• Most Negative Slack -5.00
• Sum of Negative Slack - 10.00
• Number of Critical PO 2

• sisgt read_eqn full.adder
• sisgt source script
• sisgt print
• co a b a ci b ci
• sum co' a co' b co' ci a b ci

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Example Sequential Logic (1)

• sisgt read_kiss mark1.kiss2
• mark1.kiss2 pi 5 po16 nodes 0 latches 0
• lits(sop) 0 lits(fac) 0 states(STG) 16
• sisgt state_minimize stamina
• Running stamina, written by June Rho, University
  of Colorado at Boulder
• Number of states in original machine 16
• Number of states in minimized machine 12
• mark1.kiss2 pi 5 po16 nodes 0 latches 0
• lits(sop) 0 lits(fac) 0 states(STG) 12

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Example Sequential Logic (2)

• sisgt state_assign jedi
• mark1.kiss2 pi 5 po16 nodes 20 latches 4
• lits(sop) 195 lits(fac) 144 states(STG) 12
• sisgt source script
• mark1.kiss2 pi 5 po16 nodes 16 latches 4
• lits(sop) 91 lits(fac) 81 states(STG) 12
• sisgt full_simplify
• mark1.kiss2 pi 5 po16 nodes 16 latches 4
• lits(sop) 91 lits(fac) 80 states(STG) 12

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Example Sequential Logic (3)

• sisgt extract_seq_dc
• number of latches 4 depth 6 states visited
  12
• sisgt full_simplify
• mark1.kiss2 pi 5 po16 nodes 16 latches 4
• lits(sop) 79 lits(fac) 70 states(STG) 12
• sisgt extract_seq_dc
• sisgt source script.rugged
• mark1.kiss2 pi 5 po16 nodes 17 latches 4
• lits(sop) 70 lits(fac) 66 states(STG) 12

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Example Sequential Logic (4)

• sisgt retime -n
• Lower bound on the cycle time 3.40
• Retiming will minimize the cycle time
• RETIME Initial clk 13.60, Desired clk 3.40
• initial cycle delay 13.60
• initial number of registers 4
• initial logic cost 78.00
• initial register cost 4.00
• Failed at 3.40 Now attempting 8.50
• Failed at 8.50 Now attempting 11.05
• Failed at 11.05 Now attempting 12.32
• Failed at 12.32 Now attempting 12.96
• Failed at 12.96 Now attempting 13.28
• Failed at 13.28 Now attempting 13.44

• Success at 13.44, Delay is 13.40
• Success Now attempting 13.34
• Quitting binary search at 13.34
• final cycle delay 13.40
• final number of registers 8
• final logic cost 78.00
• final register cost 8.00
• RETIME Final cycle time achieved 13.40
• mark1.kiss2 pi 5 po 16 nodes 17 latches 8
• lits(sop) 70 lits(fac) 66

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Example Sequential Logic (5)

• sisgt rlib lib2.genlib
• sisgt map -s
• total gate area 104864.00
• maximum arrival time (19.75,20.35)
• mark1.kiss2 pi 5 po16 nodes 50 latches 9
• lits(sop) 120 lits(fac) 105

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Questions ??