DOM MB Implementation

1
DOM MB Implementation

• Lawrence Berkeley National Laboratory,
• Berkeley, Ca
• June 5 2002
• Gerald Przybylski

2
Introduction

• Scope
• Touch on big picture
• Concentrate on hardware to be built at LBNL
• Purpose
• Review AMANDA string 18 DOM prototype
  capabilities
• Discuss necessary and desirable changes

3
History

• 1996 ATWR based DOM by JPL not deployed
• 1997 JPL DOM deployed (gtp)
• October 1998 sausage making
• 11 month development/production cycle
• January 2000 AMAMDA string 18 deployment
• Software and firmware development
• January 2001 surface DAQ upgrade
• More software and firmware development

4
DOM Hardware Subsystems

• PMT front end and Digitizer
• Trigger comparators
• Configurable Glue Logic
• Event buffer memory (RAM)
• Communications interface
• CPU OS, Application, Deamons
• Reference oscillator clock counter
• HV Power supply control circuits
• Flasher circuits
• Power conversion and distribution
• Neighbor coincidence circuits
• Housekeeping ADCs DACs

5
Firmware Subsystems

• Trigger logic Time stamping logic
• ATWD Readout engine
• Feature extraction
• Record forming
• Data storage / retrieval state machine(s)
• Data compression
• Time calibration
• Gain calibrations, transit time measurement
• Communications engine
• Supernova hit counters
• Housekeeping

6
PMT Output Circuit

• Low noise (digital) control of PMT HV supply
• Transformer coupling for wide bandwidth and low
  stored energy
• DC Coupling from transformer to ATWD, with
  baseline restoration on high gain channels
• Multiple amplification paths (3 to ATWD inputs,
  one to FADC)
• Digitally settable pedestal
• Delay line (lumped or coax)
• Two ATWDs per module as deployed spare, or
  ping-pong, or extended high speed capture

7
Trigger Discriminators

• Two programmable thresholds redundant or trigger
  enhancements
• High speed, low power, low switching noise
• Differential output for improved noise
  performance
• Latching for stability and after-pulsing
  suppression
• Synchronous capture to avoid ambiguity

8
FPGA Glue Logic

• Altera low power part
• Schematic entry or text entry (HDL)
• Third party tools supported
• Upgrade to 100 K gate part
• CPU loads FPGA design from flash file
• Firmware development before deployment
• Firmware development after deployment

9
Data communications

• 8 bit communications DAC
• 10 bit communications ADC
• Transformer coupling
• Accommodate power pick-off
• Time tick generation
• Time tick reception
• Local custom protocol suited to our needs
• 38 kilobaud fallback / 400 kilobaud fast

10
Embedded system CPU

• ARM (Advanced RISC Machine) 32 bit, 18 MHz, 50
  mW
• Interrupt capable
• UART for fallback communications
• Foreground processing data acquisition
• Background processing, housekeeping, time
  keeping, watchdog, maintenance interface
• Boot loader in ROM (cant shoot self in foot)

11
High quality ref. clock

• 6 x 10-11 Allen Variance (bandwidth independent
  figure of merit)
• AT cut, or SC cut
• Recalibrate at intervals of seconds
• Operation near edge of compensation range
• Isothermal environment to 0.01 C
• Frequency multiply with PLL

12
PMT HV Supply control

• LBL to specify Collaborator to supply
• Digital control for noise management
• Digital readout for noise management
• Power switching circuit ground separate from
  voltage multiplier circuit ground
• Wide-band Anode output transformer
• Low stored energy
• High reliability a MUST!!

13
Flasher circuits

• Wide area flasher, a piggy-back card
• PMT calibration flasher, on board
• Programmable repetition rate
• Programmable brightness
• Independent operation
• Auto off feature (shut down after timeout)
• Create generalized interface for other possible
  applications

14
DC Power

• 100 V input
• /- 5V analog 3.3V digital 2.5V or 1.8V core Vdd,
  -8V for power supply
• Careful ground management
• Cable termination without power loss
• Pick-off communications signal without
  introducing switching noise into it.
• Peak power capacity for transients
• High reliability

15
Nearest Neighbor Signaling

• Separate Transmit to each Neighbor
• Separate Receive from each Neighbor
• Output for trigger logic (firmware)
• Input from trigger logic (firmware)
• Allow Forwarding signal if no local hit (firmware)

16
Fixes/Improvements

• Replace obsolete parts (FADC, PLD)
• 100 V power supply input (no standard product)
• Power supply noise improvement
• Power switching circuit ground separate from
  voltage multiplier ground in PMT power supply
• PMT base upgrade (digital control etc)
• Replace MUX at ATWD input 2 to reduce power
  consumption
• QFP package for ATWD smaller footprint
• ATWD design upgrades if time and funding
  permit
• Denser memory fewer parts fewer traces
• Improve layer stack-up to minimize noise

17
More Fixes/Improvements

• Quad cable Impedance change
• Communications overload recovery
• Delete fiber interface for PMT signal
• RELIABILITY Analysis and component selection for
  low failure rate
• Increase flexibility of neighbor circuit by
  adding independent transmission
• CPLD update to include better serial
  encoder/deocoder
• Embed CPU in FPGA (Altera Excalibur ARM EPXA1)
• Photo sensor activated HV shutdown circuit to
  protect PMT from room light and sun light
• Better delay line solution