CS 161Computer Architecture Chapter 5

1
CS 161Computer Architecture Chapter 5

• Instructor L.N. Bhuyan
• www.cs.ucr.edu/bhuyan
• LECTURE 10

2
Compose Datapath R-form Load/Store
Add muxes
ALU control
MemWrite
4
ReadRegister 1
Readdata
Readdata 1
Instr- uction
Zero
A L U
ReadRegister 2
MemTo- Reg0R-form1L/S
Address
Readdata 2
WriteRegister
M u x
Dmem
Registers
WriteData
WriteData
1 M u x 0
RegWrite
ALUSrc 0 R-format1 Load/Store
MemRead
SignExtend
32
16
3
Compose Datapath Imem PC
a d d
4
ALU control
MemWrite
ReadReg1
4
Read Addr
Readdata
P C
Readdata1
Zero
A L U
ReadReg2
Instruc- tion
Address
Readdata2
MemTo- Reg
WriteReg
M u x
Imem
Dmem
Registers
WriteData
WriteData
M u x
ALUSrc
RegWrite
MemRead
SignExtend
32
16
4
Compose Datapath Branch
Left Shift 2 module
M u x
a d d
4
ltlt 2
PCSrc
MemWrite
ReadReg1
Read Addr
ALUcon
P C
Readdata
Readdata1
Zero
ReadReg2
A L U
Instruc- tion
Address
Readdata2
MemTo- Reg
WriteReg
M u x
Imem
Dmem
Registers
WriteData
WriteData
M u x
ALUSrc
RegWrite
MemRead
What about jump?
32
16
5
Recap Single-Cycle Datapath
M u x
a d d
4
ltlt 2
PCSrc
MemWrite
ReadReg1
4
Read Addr
ALU con
P C
Readdata
Readdata1
Zero
ReadReg2
A L U
Instruc- tion
Address
Readdata2
MemTo- Reg
WriteReg
M u x
Imem
Dmem
Registers
WriteData
WriteData
M u x
ALUSrc
RegWrite
MemRead
Supports allMIPS-lite instrns?
32
16
6
Datapath Miscellaneous Details

• Wrinkle destination registers may differ across
  instruction formats
• R-format rd lt- rs op rt add t0,s0,s1,
  For this instn, bits 11-15 is destination (t0),
  which should be connected to the write reg.
• I-format rt lt- memrs imm16 lw t0,24(s
  3), For this instn, bits 16-20 should go to the
  write port. Bits 0-15 go to the ALU as address.
• Connection to the write port changes!
• Solution? mux to the rescue!

7
Datapath (add RegDst Mux)
M u x
a d d
4
ltlt 2
PCSrc
MemWrite
2521
ReadReg1
Read Addr
P C
Readdata
Readdata1
Zero
ReadReg2
310
2016
A L U
Instruc- tion
Address
Readdata2
M u x
MemTo- Reg
WriteReg
M u x
Dmem
Imem
Regs
ALU- con
WriteData
WriteData
1511
M u x
RegDst
ALU- src
RegWrite
MemRead
150
8
Datapath Miscellaneous Details

• What if instruction is a conditional branch
  (beq)?
• if operands equal, take branch (PC gets
  PC4offset)
• else PC gets PC4
• Therefore, set control point PCSrc 1 if and
  only if beq and Zero asserted

9
Datapath (add Branch control point)
M u x
a d d
ltlt 2
4
PCSrc
MemWrite
2521
ReadReg1
Branch
Read Addr
P C
Readdata
Readdata1
Zero
ReadReg2
310
2016
A L U
Instruc- tion
Address
Readdata2
M u x
MemTo- Reg
WriteReg
M u x
Dmem
Imem
Regs
ALU- con
WriteData
WriteData
1511
M u x
RegDst
ALU- src
RegWrite
MemRead
150
10
Adding Control

• CPU Datapath Control
• Single-Cycle Design
• Instruction takes exactly one clock cycle
• Datapath units used only once per cycle
• Writable state updated at end of cycle
• What must be controlled?
• Multiplexors (Muxes)
• Writable state elements Register File, Data
  Memory (Dmem)
• what about PC? Imem?
• ALU (which operation?)

11
Processor Datapath Control

• Single-Cycle Design everything happens in one
  clock cycle ? until next falling edge of
  clock, processor just one big combinational
  circuit!!! ? control is just a
  combinational circuit(output, just function of
  inputs)
• outputs? control points in datapath
• inputs? the current instruction! (opcode, funct
  control everything)

12
Defining Control
op rs rt rd shamt
funct
R-format instruction
6
6
Control Logic
To datapath
13
Defining Control

• Note that funct field only present in R-format
  instruction - funct controls ALU only
• To simplify control, define Main, ALU control
  separately using multiple levels will also
  increase speed important optimization technique
• ALUop inputs will be defined

MainControl
op
opfunct
ControlLogic
ALU- con
ALUop
funct
14
Defining ALU Control
ALUcon
A B
A L U
Zero Result
15
Defining ALU Control
ALUOp Funct Fielda1 a2 f5 f4 f3 f2 f1 f0 ALU
con 0 0 x x x x x x 0010 x 1 x x x x x x
0110 1 x x x 0 0 0 0
0010 1 x x x 0 0 1 0 0110 1 x x x 0 1 0 0
0000 1 x x x 0 1 0 1 0001 1 x x x 1 0 1
0 0111
Dont Cares
16
Deriving ALUcon outputs

• From the truth table, output signals can be
  easily derived because of dont cares.
• Operation2 (msb) ALUOp0 OR (ALUOp1 AND F1)
• Operation1 ALUOp1 NOR F2
• Operation0 (lsb) ALUOp1 AND (F3 OR F0)
• ALUOp is supplied by the main control unit (to be
  designed) and F0-F5 are the lsbs of the
  instruction.

17
Fully Minimized ALU Control
A
L
U
O
p
A
L
U
O
p
0
A
L
U
O
p
1
O
p
e
r
a
t
i
o
n
2
F
3
ALUcon 4th bit0
F
2
O
p
e
r
a
t
i
o
n
1
funct
F
1
O
p
e
r
a
t
i
o
n
0
F
0
18
Datapath ALU Control
M u x
a d d
ltlt 2
4
PCSrc
MemWrite
ReadReg1
Read Addr
P C
Readdata
Readdata1
Zero
ReadReg2
A L U
Instruc- tion
Address
Readdata2
MemTo- Reg
WriteReg
M u x
Imem
Dmem
Registers
ALU- con
WriteData
WriteData
M u x
ALU- src
ALU Control
RegWrite
MemRead
Instr50
ALUOp
19
Implementing Main Control
Main Control has one 6-bit input, 9 outputs (7
are 1-bit, ALUOp is 2 bits) To build Main
Control as sum-of-products (1) Construct a
minterm for each different instruction (or
R-type) each minterm corresponds to a single
instruction (or all of the R-type instructions),
e.g., MR-format, Mlw(2) Determine each main
control output by forming the logical OR of
relevant minterms (instructions), e.g., RegWrite
MR-format OR Mlw
Main Control
RegDstBranchMemReadMemtoRegALUopMemWrite
ALUSrcRegWrite
op
2
20
Single-Cycle MIPS-lite CPU
M u x
a d d
ltlt 2
4
PCSrc
MemWrite
2521
ReadReg1
Branch
Read Addr
P C
Readdata
Readdata1
Zero
ReadReg2
310
2016
A L U
Instruc- tion
Address
Readdata2
M u x
MemTo- Reg
WriteReg
M u x
Dmem
Imem
Regs
ALU- con
WriteData
WriteData
1511
op3126
M u x
RegDst
ALU- src
ALU Control
RegWrite
MemRead
Main Control
150
50
ALUOp
21
Adding Jal instrn to datapath

• Jal consists of jump and link for function calls
  jump to the function address (j target) already
  implemented in Fig. 5.29
• Place PC4 (return address) in ra. So (a) extend
  the mux at reg input to include 31 (ra) as
  another input and (b) expand the mux at write
  data input to have PC4 as another input. DRAW on
  Fig. 5.29.