M68K Assembly Language Programming

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M68K Assembly Language Programming

• to accompany the Motorola 68000 Assembly Language
  Programming text, by Bob Britton

Notice Slides in this series originally,
provided by B.Britton, have been modified by
R.Renner to reflect Spring 2006 course content.
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Benefits of Studying Assembly Language Programming

• Obtain Insights into writing more efficient code
• Will become familiar with what compilers do
• Acquire an understanding of how a CPU is
  organized down to the functional component level
• Open new opportunities in the field of embedded
  processors

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• Cisco Routers,
• Laser Printers built by HP and Fuji Xerox,
• PDAs,
• Set-Top Boxes,
• Sony AIBOTM Entertainment Robot (64bit RISC),
• Minolta Digital Camera.
• Sony PlayStation,
• TurboMan (M68K)

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MOTOROLA 68000 History

• The M68Kis a Complex Instruction Set (CISC)
  microprocessor from Motorola released in the
  1980's.
• Fabricated with approximately 68,000 Transistors.
• As its clock rate increased it was used for the
  design of computers like the Apple Macintosh,
  Amiga and Atari and the original Sun Microsystems
  UNIX machines as well as the Apollo/Domain
  workstations.
• Now mainly used in low cost embedded systems

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MC68000

• MC68000 Low Cost 32-Bit Microprocessor
• The industry's lowest cost 32-bit microprocessor
• MC68HC000 (and C001) is a CMOS version of the
  original MC68000
• The MC68EC000 version provides a lower cost
  68000 solution
• The MC68SEC000 version provides a static, low
  power implementation consuming only 15.0mA in
  normal 3.3V operation and 0.5mA in static standby
  mode.

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MC68000 Features

• 32 Bit Data and Address Registers
• 16 MByte Direct Addressing Range
• 56 Powerful Instructions
• Memory Mapped Input/Output
• 14 Addressing Modes
• 2 MIPS at 20MHz
• Available in 8, 10, 12, 16 20 MHz speeds
  (MC68HC000 and MC68EC000)
• Available in 10, 16 20 MHz speeds (MC68SEC000)
• Available in 8, 10, 12 16 MHz speeds
  (MC68HC001)

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M68020 Features

• 4 GByte Direct Linear Address Space
• 32 Bit Address and Data Buses
• 256 Byte Instruction Cache
• 10 MIPS _at_ 33 MHz
• Available in 16, 20, 25, and 33 MHz
• MC68EC020 Available in 16 and 25 MHz

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RISC History

• The long and short of it is that for any given
  level of general performance, a RISC chip will
  typically have many fewer transistors dedicated
  to the core logic. This allows the designers
  considerable flexibility they can, for instance
• increase the size of the register set
• implement measures to increase internal
  parallelism
• add huge caches
• add functionality like I/O and timers for
  microcontrollers
• add vector (SIMD) processors like AltiVec
• build the chips on older lines, which would
  otherwise go unused
• do nothing offer the chip for battery-constrained
  or size-limited applications

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Features of a RISC Architecture

• uniform instruction encoding (e.g. the op-code is
  always in the same bit positions in each
  instruction, which is always one word long),
  which allows faster decoding
• a homogeneous register set, allowing any register
  to be used in any context and simplifying
  compiler design (although there are almost always
  separate integer and floating point register
  files)
• simple addressing modes (complex addressing modes
  are replaced by sequences of simple arithmetic
  instructions).
• few data types supported in hardware (for
  example, some CISC machines had instructions for
  dealing with byte strings. Others had support for
  polynomials and complex numbers. Such
  instructions are unlikely to be found on a RISC
  machine).

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MIPS History

• In 1981, a team led by John Hennessy at Stanford
  University started work on what would become the
  first first MIPS processor. The basic concept was
  to dramatically increase performance through the
  use of deep instruction pipelines.
• Generally a pipeline spreads out the task of
  running an instruction into several steps, and
  then start working on "step one" of an
  instruction even before the preceding instruction
  is complete. In contrast, traditional designs of
  the era waited to complete the entire instruction
  before moving on, thereby leaving large areas of
  the CPU idle as the process continued.

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The R4000 series, released in 1991, extended
theMIPS instruction set to a full 64-bit
architecture, moved the FPU onto the main die to
create a single-chip system, and operated at a
radically high internal clock speed. The R8000
(1994) was the first superscalar MIPS design,
able to execute two ALU and two memory operations
per cycle. MIPS cores have been very
successful, they form the basis of many newer
Cisco routers, cable modems and ADSL modems,
smartcards, laser printer engines, set-top boxes,
hand-held computers, and the Sony PlayStation
2. In 1997 the 48th million MIPS-based CPU
shipped, making it the first RISC CPU to outship
the famous Motorola 68000 family.
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Freescale's Coldfire

• 1994 RISC w/subset of 68K instruction set
• small inexpensive Linux support
  auto.industry
• ColdFire processors are a potent force in the
  32-bit market. 68K heritage, aggressive
  pricing/performance points, highly integrated
  standard products, and comprehensive development
  tools support, Freescale's ColdFire architecture
  will drive the 68K Family into the future.
• -- freescale.com

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ARM History

• Design began in 1983 (Acorn Computers, Ltd) -gt
  MOS technology
• Advanced RISC Machines (ARM)
• 32-bit data bus 16-bit address bus 16 registers
• ARM core has only 30,000-35,000 transistors!
• simplicity, with high performance low cost
• ex Apple Newton PDA, cell phones, routers,
  calc...
• gt 75 of all 32-bit embedded CPUs