Pipelining

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Pipelining

• Andreas Klappenecker
• CPSC321 Computer Architecture

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Basic Idea
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Time Required for Load Word

• Assume that a lw instruction needs
• 2 ns for instruction fetch
• 1 ns for register read
• 2 ns for ALU operation
• 2 ns for data access
• 1 ns for register write
• Total time 8 ns

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Non-Pipelined vs. Pipelined Execution
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Question

• What is the average speed-up for
• pipelined versus non-pipelined execution
• in case of load word instructions?

Average speed-up is 4-fold!
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Reason

• Assuming ideal conditions
• time between instructions (pipelined)
• time between instructions (nonpipelined)
• number of pipe stages

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MIPS Appreciation Day

• All MIPS instructions have the same length
• gt simplifies the pipeline design
• fetch in first stage and decode in second stage
• Compare with 80x86
• Instructions 1 byte to 17 bytes
• Pipelining is much more challenging

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Obstacles to Pipelining

• Structural Hazards
• hardware cannot support the combination of
  instructions in the same clock cycle
• Control Hazards
• need to make decision based on results of one
  instruction while other is still executing
• Data Hazards
• instruction depends on results of instruction
  still in pipeline

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Structural Hazards

• Laundry examples
• if you have a washer-dryer combination instead of
  a separate washer and dryer,
• separate washer and dryer, but roommate is busy
  doing something else and does not put clothes
  away sic!
• Computer architecture
• competition in accessing hardware resources,
  e.g., access memory at the same time

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Control Hazards

• Control hazards arise from the need to
• make a decision based on results of an
• instruction in the pipeline
• Branches What is the next instruction?
• How can we resolve the problem?
• Stall the pipeline until computations done
• or predict the result
• delayed decision

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Stall on Branch

• Assume that all branch computations are done in
  stage 2
• Delay by one cycle to wait for the result

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Branch Prediction

• Predict branch result
• For example, predict always that branch
• is not taken
• (e.g. reasonable for while instructions)
• if choice is correct, then pipeline runs at full
  speed
• if choice is incorrect, then pipeline stalls

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Branch Prediction
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Delayed Branch
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Data Hazards

• A data hazard results if an instruction depends
  on the result of a previous instruction
• add s0, t0, t1
• sub t2, s0, t3 // s0 to be determined
• These dependencies happen often, so it is not
  possible to avoid them completely
• Use forwarding to get missing data from internal
  resources once available

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Forwarding

• add s0, t0, t1
• sub t2, s0, t3

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Single Cycle Datapath
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Pipelined Version