TELECOMMUNICATIONS

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TELECOMMUNICATIONS

• Dr. Hugh Blanton
• ENTC 4307/ENTC 5307

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• The phase lock loop (PLL) is a frequency
  selective feedback system which can synchronize
  with a selected input signal and track the
  frequency changes associated with it.

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• The basic PLL system is comprised of three
  essential blocks
• A phase detector,
• A loop filter, and
• A voltage-controlled oscillator (VCO).

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Phase Detector

• The phase detector compares the phase of the
  periodic input signal Vs(t) with the output
  frequency of VCO and generate an error voltage
  Vd(t).
• The error voltage is then filtered by the loop
  filter and is applied to the VCO in the form of
  the voltage Ve(t) to control the frequency of
  oscillation.

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• When the PLL is locked on the input signal
  (normal PLL operation), the VCO frequency is
  identical to the input frequency fs, except for
  finite phase difference, qo.
• This net phase difference of phase error, qo, is
  necessary to generate the corrective error
  voltage, Ve(t), to shift the VCO frequency to
  higher frequencies if fs starts to increase, or
  to lower frequencies if fs starts to decrease in
  order to maintain lock.

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• The figure shows the case when the input
  frequency is equal to wo (the so called
  free-running frequency) and increases to 2wo.

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• The self-correcting ability of the system allows
  the PLL to track the frequency changes of an
  input signal, once it is locked.
• The range of frequencies over which the PLL can
  maintain lock with the input is defined as the
  lock range.
• The lock range cannot exceed the range of control
  of the VCO.

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• Lock does not exist all the time.
• With no input signal applied to the PLL, the
  filtered error voltage Ve(t) in the feedback loop
  is equal to zero.
• Thus, the PLL operates at the free-running
  frequency

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• If a periodic input signal Vs(t) is applied to
  the PLL such that ws is sufficiently close to wo,
  the feedback nature of the PLL causes an error
  voltage Ve(t) to be generated.
• The forces the VCO to synchronize with the input
  frequency, and the PLL will be locked.

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• The range of frequencies over which the PLL can
  acquire lock with the incoming signal is called
  the capture range or (acquisition range).
• The capture range is always smaller than the lock
  range.

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• When the PLL is locked, the VCO output provides a
  periodic waveform which is at the same exact
  frequency as the input signal, except for a
  finite difference qo, which is the phase
  difference necessary to generate Ve to keep the
  PLL in lock.

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• If the input signal includes many frequency
  components and noise and other disturbances, the
  PLL will be locked on one component (closest to
  wo).
• The frequency output of PLL will regenerate this
  particular component eliminating the other
  undesired frequencies.

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• Assume that the PLL is opened between the loop
  filter output and the VCO control input.
• This would cause the error voltage to be
  artificially reduced to zero, and the VCO will
  continue to oscillate at the free-running
  frequency, fo.

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• Let the input signal of fs (fs gt fo, yet close to
  fo) be applied.
• Since the phase detector normally functions as a
  mixer, the output of the phase detector will be
  two frequency components,
• a sum frequency (fsum fo fs) and
• a difference frequency (Df fo fs).
• Any mixer can be used as a phase detector.

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• The loop filter is a narrow-band low pass filter
  that filters fsum leaving the difference
  frequency (Df fo fs).
• If fs is close to fo, the difference frequency
  will appear at the output of the loop filters as
  a sinusoidal beat note.

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• If the loop is closed, the VCO frequency will be
  modulated by the beat note.
• Df becomes a function of time.

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• The portion of the beat note that modulates the
  VCO closer to the input signal appears more
  rounded, and the portion that modulates the VCO
  away from the input signal appears more peaked.
• Because of the asymmetry, the beat note contains
  a finite DC voltage which steadily pushes the VCO
  frequency toward the input signal.

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• As the VCO drifts toward fs, the beat note
  frequency rapidly decreases, the asymmetry
  increases, and the transient rapidly converges to
  a steady-state DC value, corresponding to the
  lock condition where the VCO frequency is exactly
  equal to fs.

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• Once the system is locked, the difference Df is
  identically equal to zero, and only a DC voltage
• generated by the phase difference between the
  VCO output and the input signal, remains at the
  loop filter output.
• It is assumed that the detector characteristic
  has a gain of Kd(V/rad), and the filter has unity
  gain at DC.

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• The total time taken by the PLL to establish lock
  is called pull-in time.

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