Decoding in Optics

1
Decoding in Optics

• Saied HematiPh.D. Candidate
• BCWS Centre, Dept. Systems Computer Eng.
  Carleton UniversitySupervisor Amir H.
  Banihashemi

2
outline

• Introduction
• Coding in high speed applications
• Sum-Product Algorithm (SP)
• Electro-optical implementation of SP
• Conclusion

3
Introduction

• Turbo Codes and LDPC Codes can approach the
  capacity of many channels within hundredths of a
  dB.
• Decoding of these codes is computationally
  demanding since numerous iterative floating point
  computations are required.
• Digital and Analogue VLSI implementations have
  already been reported.
• For high speed applications, implementation is
  more challenging.
• We show that iterative decoding algorithms can be
  implemented by using electro-optical devices.

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Coding in High Speed Application

• Error control coding is required in communication
  systems to improve error rate.
• Reed-Solomon and convolutional codes are
  conventional FEC schemes in optical links.
• More advanced coding schemes have been proposed.
  Complexity however, is always a concern.
• Using hard-decision algorithms is known to cause
  2-3 dB degradation in performance.
• State of the art transmission technology in
  optical communications (DWDM)
• 256 40Gbit/s ( 10.2Tbit/s) over 100 km
  (Alcatel)
• 27340Gbit/s ( 10.9Tbit/s) over 117 km (NEC)

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Sum-Product Algorithm

• Sum- Product (SP) is an iterative decoding
  algorithm, which works with soft information and
  can be applied to the state of the art coding
  schemes (Turbo Codes, LDPC codes,).
• SP is theoretically suboptimal, but the gap to
  optimal decoding is small in practice.
• Implementing the SP algorithm is considered too
  complex in high speed applications, particularly
  for large block lengths and at low to moderate
  SNRs.

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Sum-Product Algorithm

• Iterative decoding can be most naturally
  described using graph representations.
• For linear block codes, there are mainly two
  types of nodes in terms of their computations
• - Variable nodes (VAR)
• - Parity Check nodes (CHK)

Check Nodes I II III
1 2 3 7 6
5 4
Variable Nodes
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Sum-Product Algorithm

• Soft information along each edge is
  represented by non-negative real numbers p0 and
  p1, reflecting the probabilities of the variable
  node connected to the edge being zero or one,
  respectively (p0 p1 1).
• For nodes with degrees larger than three, a
  cascade of above operations can be used.

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Sum-Product Algorithm

• Digital implementation of SP
• - Straightforward (Design
  Fabrication)
• - High precision modules can be built
• - High power area consumption
• - Large delay due to high order CHK and
  VAR modules
• - Iterative nature makes it slow
• Analogue implementation of SP
• - Moderate precision can be achieved
• - Design is more complex (Subthreshold
  design)
• - Fabrication might be more expensive (
  BiCMOS)

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Sum-Product Algorithm

• - Non-ideal performance of transistors
  limits the speed and
• accuracy
• - Higher speed (iteration disappears)
• - Lower power consumption
• - Lower area consumption
• Analogue electro-optical implementation
• - Technology is not mature enough
• - More expensive
• - Very high speed performance can be
  achieved

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Electro-Optical implementation

• Linear Y-fed Optical Directional Coupler
• -two optical wave-guides are brought in close
  proximity with each other over an interaction
  length and coupling occurs between the optical
  modes of the two wave guides. A single mode input
  wave-guide feeding a symmetric Y- junction
  connected to a directional coupler.
• - when a non-zero voltage is applied to the
  electrodes, causes unequal splitting of light
  between the outputs.
• - recently, a very linear modulation curve
  has been reported.
• IO1/Iin 0.5 aV
• IO2/Iin 0.5 aV

V
Io1
Iin
Io2
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Electro-Optical implementation

• By selecting V (0.5-p)/a
• IO1/Iin p
• IO2/Iin 1 p p
• p-p splitter is the basic building block
  for implementing CHK and VAR modules

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Electro-Optical implementation
Parity Check Module (CHK)
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Electro-Optical implementation
Variable Module (VAR)
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Electro-Optical implementation
q0
p0
xp0q0
C(p0q0p1q1)
PDA
xp0
xp0q1
PDA
X
C(p0q1p1q0)
xp1q0
xp1
xp1q1
Parity Check Module, input and outputs are
electrical signals PDA Photo Diode Array
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Electro-Optical implementation
Photo diode
q0
combiner
C(p0q0p1q1)
p0
q1
C(p0q1p1q0)
p1
Parity Check Module
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Conclusion

• Linear Y-fed Optical Directional Coupler is a
  good candidate for implementing very high speed
  iterative decoders.
• All necessary components can work up to several
  hundred GHz.
• Associated delay in modules with several inputs
  is very small.
• These components can be integrated and fabricated
  on a small substrate.
• Having a high speed iterative decoder can pave
  the way for using advanced coding schemes in long
  haul optical communications.
• Application of such decoders is not limited to
  optical communication.
• Electrical part of this circuit limits the final
  speed.
• We here assumed that we have P0 and P1, but in
  general we need another block for obtaining these
  number from the received signal.