Register vs Latch vs SRAM

1
Register vs Latch vs SRAM
2
Delay vs. Drive Strength

• Cell Area rise_delay fall_delay
• inv_a1 9.4 318ps 192ps
• inv_a4 15.68 241ps 140ps
• inv_a8 47.04 200ps 100ps
• nand2_a1 12.54 375ps 228ps
• nand2_a4 28.22 207ps 166ps
• nor2_a1 12.54 440ps 173ps
• nor2_a4 28.22 338ps 123ps

3
Distribution of Gates (DMA)

• Leaf Cell Count
  Area
• and2_a1 642
  6214.5600
• and2_a2 42
  487.8720
• and3_a1 131
  1521.6960
• and3_a2 13
  201.3440
• aoi21_a1 180
  1742.4000
• aoi21_a2 15
  290.4000
• aoi22_a1 315
  3659.0400
• aoi22_a2 9
  209.0880
• buf_a1 130
  1006.7200
• buf_a2 350
  3388.0000
• buf_a4 295
  4568.9600
• inv_a1 1371
  7962.7680
• inv_a2 391
  3027.9040
• inv_a4 443
  5145.8880
• muxi2_a1 261
  4042.3680
• muxi2_a2 22
  425.9200
• nand2_a1 811
  6280.3840
• nand2_a2 247
  2869.1520

• or3_a2 1
  25.1680
• w_and2_a4 52
  1208.0640
• w_and3_a4 3
  92.9280
• w_aoi21_a4 3
  116.1600
• w_buf_a16 14
  758.9120
• w_buf_a8 27
  731.8080
• w_dff0_a2 221
  9412.8320
• w_dff1_a2 1054
  57135.2320
• w_inv_a16 13
  553.6960
• w_inv_a32 1
  81.3120
• w_inv_a8 74
  1719.1680
• w_muxi2_a4 5
  193.6000
• w_nand3_a2 16
  309.7600
• w_nand3_a4 5
  174.2400
• w_nand4_a2 81
  1881.7920
• w_nand4_a4 3
  127.7760
• w_nor2_a4 112
  2601.9840
• w_nor3_a4 1
  38.7200
• w_nor4_a4 3
  185.8560

4
Static Timing Analysis (DMA)

• U6365/Q (and2_a1) 0.18
  1.95 r
• U8360/Q (nand2_a4) 0.07
  2.02 f
• U2034/Q (w_or2_a4) 0.12
  2.15 f
• U8621/Q (inv_a2) 0.03
  2.18 r
• U6362/Q (nand2_a1) 0.06
  2.24 f
• U6363/Q (inv_a2) 0.08
  2.32 r
• U8458/Q (nand2_a4) 0.06
  2.38 f
• U8620/Q (inv_a2) 0.03
  2.41 r
• U6360/Q (nand2_a1) 0.06
  2.47 f
• U6361/Q (inv_a2) 0.05
  2.52 r
• U2038/Q (and2_a2) 0.11
  2.63 r
• U6358/Q (nand2_a1) 0.07
  2.69 f
• U6359/Q (inv_a2) 0.08
  2.77 r
• U8457/Q (nand2_a4) 0.06
  2.83 f
• U5187/Q (inv_a1) 0.05
  2.88 r
• U6356/Q (nand2_a1) 0.06
  2.94 f
• U6357/Q (inv_a2) 0.08
  3.02 r
• U8456/Q (nand2_a4) 0.07
  3.09 f
• U8395/Q (w_nor2_a4) 0.06
  3.15 r

• Startpoint dp_rx_pkt_adr_ff_reg_1A
• (rising edge-triggered flip-flop
  clocked by clk)
• Endpoint dp_rx_pkt_adr_ff_reg_25A
• (rising edge-triggered flip-flop
  clocked by clk)
• Path Group clk
• Path Type max
• Point Incr
  Path
• ------------------------------------------------
  ---------------
• clock clk (rise edge) 0.00
  0.00
• clock network delay (ideal) 0.00
  0.00
• dp_rx_pkt_adr_ff_reg_1A/CK (w_dff1_a2) 0.00
  0.00 r
• dp_rx_pkt_adr_ff_reg_1A/Q (w_dff1_a2) 0.31
  0.31 r
• U6194/Q (w_sbuf_a8) 0.10
  0.41 r
• U8354/Q (nand2_a4) 0.06
  0.47 f
• U8691/Q (inv_a4) 0.04
  0.51 r
• U8455/Q (nand2_a4) 0.05
  0.56 f
• U8619/Q (inv_a2) 0.06
  0.62 r
• U8355/Q (nand2_a4) 0.05
  0.67 f