The Title of your DoVo presentation

1
Networks-on-Silicon A New Paradigm for Embedded
Systems
Jef van Meerbergen Fellow Philips Research Prof.
TU Eindhoven
2
Outline

• Application scope Ambient Intelligence
• Current approach platform based design
• New approach Networks-on-Silicon
• First example in silicon multiwindow TV
• Conclusions

3
Home connected to the world
Information Productivity
Wireless
Games
Cable
Home Control
gateway
Convenience
Security
Safety
Wireless
Utility
4
Ambient Intelligence, the concept

• An environment that is sensitive, adaptive and
  responsive to the presence of people or objects
• An environment where technology is embedded,
  hidden in the background
• An environment that will preserve security,
  privacy and trustworthiness while utilizing
  information when needed and appropriate.

People to the foreground, technology to the
background

• Ubiquitous communications
• Distributed computing
• Intelligent interfaces

Boekhorst
5
Silicon implementation
TIVO

• Application oriented
• smart devices
• adaptable to env.
• real-time DSP

implemented in silicon
1 cm2 1V 1 W 10 Euro
not a Pentium but a domain specific and
programmable SoC
6
Computational efficiency
design space spanned by different types of cores
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Different architecture
100 ?W
1 mW
10 mW
100 mW
1 W
Battery powered
line powered
Powered from environment (scavenging)

• Sensor radio
• 1..10 Mtr
• Direct mapping of the SFG
• Very fast HW design

• High flexibility
• gt100 Mtr exploit ITRS
• Platform based
• Incremental SW design

8
Current platforms DVP example
A template for reuse of IP (hw sw)
via standardisation of the communication
Programmable CPUDSP cores
Application specific cores differentiating facto
r
3 busses bridges memory bottleneck
9
Current platforms DVP/Viper example (PNX8500)

• ASB and DTV
• domain specific
• and programmable
• 0.18 ?m / 8M
• 1.8V / 4.5 W
• 75 clock domains
• 35 M transistors

Santanu Dutta
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Limitations of current platforms programming
issues

• Communication via external memory under
  synchronisation control of the CPU

• coarse grain functions (frame), bandwidth
• mapping problems central resource limits
  scalability, specially with real-time constraints

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Limitations of current platforms VLSI design
issues

• wiring is dominant

• Clock distribution skew control increasingly
  difficult

12
Levels of IC architecture shift every 7- 8 years
Networks-on-Silicon Communication centric
separation of concerns
Multi-processor Platform based
design architectures Reuse of IP
Embedded processors HLS SW-compilers ILP,
VLIW
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Networks-on-Silicon

• Multistage network graph structure with routers
  and links
• Hierarchical architecture with autonomous
  clusters of processors and (local) memories

Example with 16 embedded cores programmable,
ASIPs, memories, subsystems
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Networks-on-Silicon layout issues

• Predictable wiring fabric (e.g. FPGA-like) for
• signal integrity
• timing closure
• leads to architectures with
• moderate frequency
• 500 MHz
• blocksize
• 4 Mtr.3.5mm2 in 70nm
• Mips(0.8 mm2)memory)
• Example RAW MIT

15
Networks-on-Silicon layout issues
Khatri,Brayton,Sangiovanni
Below 100nm isochronous zones lt 22 mm2 gt GALS
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Networks-on-Silicon layout issues
Application specific IP blocks with different
shapes
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Networks-on-Silicon layout issues

• Reducing the number of hops
• Different segment lengths
• Hierarchical network

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Networks-on-Silicon OSI Protocols
learn from network literature but NOS must be
more predictable to avoid time-consuming design
iterations
Application layer
Presentation layer
programming
Session layer
End-to-end services over connections guaranteed
best effort services Aethereal
Transport layer
Network layer
VLSI design
Data link layer
Physical layer
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Example Multi-window display (CPA)
PC like windows with variable sizes and shapes
e.g. PIP, TXT, OSD
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Example Multi-window display (CPA)
mem
Video In1
NR
HSRC
VSRC
mix
100Hz
Peak
Matrix
Video In2
NR
HSRC
VSRC
mix
Txt gen
mem
HSRC
VSRC
mem

• nodes limited number of well
• known weakly programmable tasks
• graph represents 1 application
• 50 ... 100 applications
• run-time switching between applic.

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CPA example Domain analysis
mem
Application graph gt subgraphs gt tasks

set of closely coupled tasks
Video In1
NR
HSRC
VSRC
mix
100Hz
Peak
Matrix
Video In2
NR
HSRC
VSRC
mix
Txt gen
mem
HSRC
VSRC
mem

• processing power Gops
• bandwidth between tasks GB/s
• 11 internal streams
• 20 external streams to mem
• 5 IO streams
• asynchronous

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CPA example architecture

• processors scalers,
• juggler, blender,
• noise reduction,
• sharpness enh.
• programmable com-
• munication network
• small grainsize
• gt 32 pixels
• blocking when
• fifos full/empty
• programmable invers
• network for sync

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CPA example TST network
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CPA example run-time reconfiguration
blanking
time
Task 1
time
Video stream 1
Task 2
time
Task 3
blanking
Task 4
Video stream 2
Task 5
Task 6
Overlap between the old and the new application
graph
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CPA chip
0.35 ?m 3.3 V 5 W 10 GOPS 7.6 Mtrans 13 x13 mm2
SE
S2MEM MEM2S JUGGLER
NR
OUT
RC
video
IN
CC
VS
SDRAM
HS
INT
CPU
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Embedded Systems Design objective
CPA
7400
Turbosparc
604e
604
604e
21364
601
21164a
microsparc
Ultra sparc
i386SX
P6
i486DX
Super sparc
P5
68040
design space spanned by different types of cores
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Conclusions

• Embedded systems are designed for a high
  computational efficiency.
• Networks-on-Silicon are the next design paradigm.
• Emphasis shifts from computation to
  communication.
• There are many similarities with existing
  networks but
• There are also differences because
  Networks-on-Silicon will be more predictable
• by using moderate block sizes, moderate
  frequencies and a predefined routing strategy
• by offering two types of services guaranteed
  throughput and best effort.
• CPA design is shown as a first silicon example.
• It demonstrates the possibilities to combine
  efficiency with flexibility.